CPSC 121: Models of Computation Module 8: Sequential Circuits - PowerPoint PPT Presentation

CPSC 121: Models of Computation Module 8: Sequential Circuits

Module 8: Sequential Circuits By the start of class, you should be able to Trace the operation of a DFA (deterministic finite- state automaton) represented as a diagram on an input, and indicate whether the DFA accepts or rejects the input. Deduce the language accepted by a simple DFA after working through multiple example inputs. CPSC 121 – 2018W T1 2

Module 8: Sequential Circuits Quiz 8 feedback: Well done. Many fine answers to the push-button light question. We will revisit this problem soon. CPSC 121 – 2018W T1 3

Module 8: Sequential Circuits CPSC 121: the BIG questions: ? ? ? 1. How can we build a computer that is able to ? ? execute a user-defined program? a) Computers execute instructions one at a time. ? ? b) They need to remember values, unlike the circuits you ? ? designed in labs 1, 2, 3 and 4. ? c) That is, a computer is a very large and very complicated sequential circuit . ? ? ? ? ? ? ? CPSC 121 – 2018W T1 4

Module 8: Sequential Circuits By the end of this module, you should be able to: Translate a DFA into a sequential circuit that implements the DFA. Explain how and why each part of the resulting circuit works. CPSC 121 – 2018W T1 5

Module 8: Sequential Circuits Announcements: Pre-class quiz #9 is due Monday November 12 th at 19:00. Textbook sections: Epp, 4th edition: 5.1 to 5.4 Epp, 3rd edition: 4.1 to 4.4 Rosen, 6th edition: 4.1, 4.2 Rosen, 7th edition: 5.1, 5.2 Assignment #4 is due tomorrow at 19:00. CPSC 121 – 2018W T1 6

Module 8: Sequential Circuits Announcements (continued): Midterm #2: Friday at 17:30 Same locations as for midterm #1. No notes, textbook, calculator or other electronic equipment is allowed. We will supply the parts of Dave’s excellent formula sheet that you need for the midterm. Covers from predicate logic (with both types of quantifiers) up to the end of today’s class, as well as labs 4, 5, 6, 7. CPSC 121 – 2018W T1 7

Module 8: Sequential Circuits Announcements (continued): Pre-class quiz #10 is tentatively due Monday November 26 th at 19:00. Textbook sections: Epp, 4th edition: 6.1, 7.1 Epp, 3rd edition: 5.1, 6.1 Rosen, 6th edition: 2.1, 2.3 up to the top of page 136. Rosen, 7th edition: 2.1, 2.3 down to the bottom of page 141. CPSC 121 – 2018W T1 8

Module 8: Sequential Circuits Module Summary Latches, toggles and flip-flops. Using a DFA for branch prediction. Other problems and exercises. CPSC 121 – 2018W T1 9

Module 8.1: Latches, toggles and flip-flops There are two types of Finite-State Automata: Those whose output is determined solely by the final state (Moore machines). Used to match a string to a pattern. Input validation. Searching text for contents. Lexical Analysis : the first step in a compiler or an interpreter. (define (fun x) (if (<= x 0) 1 (* x (fun (- x 1))))) ( define ( fun x ) ( if ( <= x 0 ) 1 ( * x ( fun ( - x 1 ) ) ) ) ) CPSC 121 – 2018W T1 10

Module 8.1: Latches, toggles and flip-flops Those that produce output every time the state changes (Mealy machines). Examples: Traffic lights controller. The push button example from quiz 8b. Button pressed Light OFF Light ON Button pressed Predicting branching in machine-language programs CPSC 121 – 2018W T1 11

Module 8.1: Latches, toggles and flip-flops A circuit that implements a finite state machine of either type needs to remember the current state: It needs memory. A latch A flip-flop A register (multiple side by side flip-flops with a common clock) CPSC 121 – 2018W T1 12

Module 8.1: Latches, toggles and flip-flops Recall the latch from lab #5: When en is low, the MUX retains its current value. When en is high, it changes its value to d instead. CPSC 121 – 2018W T1 13

Module 8.1: Latches, toggles and flip-flops Problem: Design a circuit that changes state every time a button is pushed. ? ? CPSC 121 – 2018W T1 14

Module 8.1: Latches, toggles and flip-flops What signal does the button generate? high low CPSC 121 – 2018W T1 15

Module 8.1: Latches, toggles and flip-flops Complete the circuit... Circuit to calculate the next state CPSC 121 – 2018W T1 16

Module 8.1: Latches, toggles and flip-flops What is wrong with our solution? a) We should have used XOR instead of NOT. b) The light will be in a random, unpredictable state. c) The delay introduced by the NOT gate is too long. d) There is some other problem with the circuit. e) Nothing is wrong. ▷ CPSC 121 – 2018W T1 17

Module 8.1: Latches, toggles and flip-flops This toll booth has a similar problem. From MIT 6.004, Fall 2002 CPSC 121 – 2018W T1 19

Module 8.1: Latches, toggles and flip-flops Instead use this: P.S. Call this a “bar”, not a “gate”, or we'll tie ourselves in (k)nots. From MIT 6.004, Fall 2002 CPSC 121 – 2018W T1 20

Module 8.1: Latches, toggles and flip-flops The circuit version of this improved tollbooth is called a flip-flop: CPSC 121 – 2018W T1 21

Module 8.1: Latches, toggles and flip-flops Assume the value stored in the flip-flop is 1 and d = 0. As long as the clock remains low: 1 0 0 0 1 CPSC 121 – 2018W T1 22

Module 8.1: Latches, toggles and flip-flops Observe that the two select input are never the same. 1 0 0 0 1 CPSC 121 – 2018W T1 23

Module 8.1: Latches, toggles and flip-flops Now the clock goes high: 0 0 0 1 1 0 CPSC 121 – 2018W T1 24

Module 8.1: Latches, toggles and flip-flops Now the clock goes low again: 0 0 0 1 0 1 CPSC 121 – 2018W T1 25

Module 8.1: Latches, toggles and flip-flops Finally we set d = 1: 0 1 1 1 0 1 CPSC 121 – 2018W T1 26

Module 8.1: Latches, toggles and flip-flops And we get the following improved circuit for our button and light problem: CPSC 121 – 2018W T1 27

Module 8: Sequential Circuits Module Summary Latches, toggles and flip-flops. Using a DFA for branch prediction. Other problems and exercises. CPSC 121 – 2018W T1 28

Module 8.2: Using a DFA for branch prediction How do computers really execute programs? Programs written in a high-level language (Racket, Java) are translated into machine language. A machine-language program is a sequence of very simple instructions. Each instruction is a sequence of 0s and 1s. Each instruction also has a human-readable version Humans don't like looking at long sequences of 0s and 1s. The human-readable version is not actually part of the program. CPSC 121 – 2018W T1 29

Module 8.2: Using a DFA for branch prediction Example (modified to make it easier to understand): (1) sum ← 0 (2) is n = 0? (3) if true go to 7 (4) sum ← sum + n (5) n ← n – 1 (6) goto 2 Some instructions like instruction 3 may tell the computer that the next instruction to execute is not the next in the sequence (4), but elsewhere (7). CPSC 121 – 2018W T1 30

Module 8.2: Using a DFA for branch prediction To speed things up, a modern computer starts executing an instruction before the previous one is finished. This means that when it is executing if true go to 7 it does not yet know if the condition is true, and hence does not know if the next instruction is sum ← sum + n or instruction number 7. CPSC 121 – 2018W T1 31

Module 8.2: Using a DFA for branch prediction We want to use a DFA to predict the branch outcome. If we guess wrong, then we will ignore some of the work that was done. We will keep track of two pieces of information: What we will predict (F = not branch, T = branch). How confident we are that we are correct (F = not very, T = very). once we know if the branch was taken, we update this information. CPSC 121 – 2018W T1 32

Module 8.2: Using a DFA for branch prediction How many states will the Finite State Automaton have? a) 2 b) 4 c) 8 d) Another value less than 8. e) Another value larger than 8. ▷ CPSC 121 – 2018W T1 33

Module 8.2: Using a DFA for branch prediction Our prediction algorithm works as follows: We are confident if the last two outcomes were the same, but not if they were different. We keep predicting one outcome until we have been wrong twice in a row. Being wrong twice in a row is the same as being wrong when we’re not confident about our prediction In this case we change prediction. CPSC 121 – 2018W T1 35

Module 8.2: Using a DFA for branch prediction Hence we get the following DFA: CPSC 121 – 2018W T1 36

Module 8.2: Using a DFA for branch prediction We can then turn this DFA into a sequential circuit, as described in Lab 8. Number the states, starting with 0, and figure out how many bits you need to store the state number. Number the inputs, starting with 0, and figure out how many bits you need to represent the input. Layout enough D flip-flops to store the state (one per bit). CPSC 121 – 2018W T1 37

Module 8.2: Using a DFA for branch prediction We can then turn this DFA into a sequential circuit, as described in Lab 8 (continued). For each state, build a combinational circuit that computes the next state (and the output, if needed) given the input. Send all those into multiplexers, and use the current state as the control signal (so you only keep the correct one). Store the next state back into the D flip-flops. CPSC 121 – 2018W T1 38