D ESIGN AND I MPLEMENTAION OF A DDR SDRAM C ONTROLLER FOR S YSTEM ON C HIP Magnus Själander 2002-12-13
Contents • Double Data Rate Interfaces • DDR SDRAM Architecture and Functionality • DDR Memory Controller • Data Resynchronization • Floorplan and Place & Route • Future Work • Conclusion MO/EAB/RTN/D Magnus Själander 2002-12-13 2
Double Data Rate Interfaces New • Data Transmissions on rising and falling edge • Data Strobe SDR Clk Advantages • Time of Flight Data D0 D1 D2 D3 D4 D5 D6 D7 • Clock Skew DDR • Pin Count Clk • Bandwidth Disadvantage Data Strobe • Synchronization Data D0 D1 D2 D3 D4 D5 D6 D7 Don't care MO/EAB/RTN/D Magnus Själander 2002-12-13 3
• • • • • SDRAM Architecture Global Data Path Sense Amplifiers 1T Memory Cells Row and Column Select Lines Four Banks 2002-12-13 Row Decoder Row Decoder 4 VDD SE * Sense Amplifiers Sense Amplifiers Column Decoder and Global Data lines Column Decoder and Global Data lines Sense Amplifiers Sense Amplifiers Row Decoder Row Decoder SE Central I/O MO/EAB/RTN/D Magnus Själander BL * BL Row Decoder Row Decoder Sense Amplifiers Sense Amplifiers Column Decoder and Global Data lines Column Decoder and Global Data lines Sense Amplifiers Sense Amplifiers Row Decoder Row Decoder WL M 1 C s BL * BL C BL
DDR SDRAM Architecture Input Buffer WEi I/O Control • 2n-prefetch Data Input Register CK, CK DMi Serial to Parallel Bank Select • Delay Lock Loop 64 Bank 1 Refresh Counter Row Decoder Output Buffer Sense AMP Row Buffer 2n-prefetch Bank 2 64 32 DQ Bank 3 CK, CK Address Register Bank 4 ADDR Column Decoder Column Buffer Latency and Burst Length Strobe Gen. Programming Register DLL DQS CK, CK WEi DMi Timing Register CK, CK CKE RAS CAS WE DM CS MO/EAB/RTN/D Magnus Själander 2002-12-13 5
DDR SDRAM Improvements SDR SDRAM • Long Delay in Column Clk Decode and Data Lines Data D0 D1 • Added a Delay Lock Loop to 7 ns 7 ns Increase Clock Frequency Read Data Clock period started available DDR SDRAM Clk Delay Delayed Clk Data D0 D1 5 ns 7 ns Clock period Read Data started available MO/EAB/RTN/D Magnus Själander 2002-12-13 6
DDR SDRAM Commands Same Commands as for Standard SDRAM • READ • WRITE • ACTIVATE • PRECHARGE • REFRESH • MRS (Mode Register Set) Added • EMRS (Extended MRS) MO/EAB/RTN/D Magnus Själander 2002-12-13 7
DDR SDRAM Memory Controller DDR SDRAM Memory Controller Command Initialize Command Data APB Data Address Core Memory Controller Command Command DQS Address Address APB Buss AHB Buss Data Strobe DDR Write Data SDRAM Data Mask AHB Write Data DQ Read Data Read Data DQeven Read Data DQodd MO/EAB/RTN/D Magnus Själander 2002-12-13 8
Core Memory Controller Initialize Initialization Initialize Command Activate/Precharge Address Address Next Command Command Address Open Banks Address Address Command Refresh Refresh Open Timing Row Enable DQS Address Address Increment Current Read/Write Read Write Address Command Boundary Command Address Command MO/EAB/RTN/D Magnus Själander 2002-12-13 9
AHB Interface AHB Interface Command Command Address Command Core Memory Sample Address Address Controller Present DQS Increment Counter Data Strobe AHB Buss AHB DDR Write Data Data Data Data Mask Core SDRAM Write Data DQ x2 Addr Addr Data Read Data DQ Read Data Buffer Even even Data Data Read Data DQ Odd odd MO/EAB/RTN/D Magnus Själander 2002-12-13 10
Arbiter DDR SDRAM Memory Controller Command AHB Buss 0 Address Data AHB I Strobe Write Data Data Mask Write Data Read Data Command Command Command Address Address Core Memory Address Controller Arbiter DQS Command DDR Command Address SDRAM Data Mask Data Strobe Address Write Data AHB Buss 1 Write Data DQ Data AHB II Strobe Write Data Read Data DQeven Read Data Read Data DQodd MO/EAB/RTN/D Magnus Själander 2002-12-13 11
Capturing the Data • Phase Shift the Data Strobe • Resynchronize the Data Clk Command NOP READ NOP Address Col n Data Strobe Data Don't care MO/EAB/RTN/D Magnus Själander 2002-12-13 12
Phase Shift the Data Strobe • Delay Lock Loop Phase Detector and Control Logic • Inverter Delay Data Strobe Data Strobe Digital Delay Line Delayed 90 o • PCB Line Delay • Programmable Delay Line with Temperature Sensing Programmable Delay Line Data Strobe Delayed 90 o Data Strobe Programmable Look Up Table Temperature Sensor MO/EAB/RTN/D Magnus Själander 2002-12-13 13
Synchronization of the Data Data Even D Q One Flip-Flop for each Flank to Sample Data Data Odd D Q Data Strobe Data Strobe Data 0 1 2 3 4 5 6 7 Data Even 0 2 4 6 Data Odd 1 3 5 7 Do not care MO/EAB/RTN/D Magnus Själander 2002-12-13 14
Synchronization of the Data Continued Reference Clock Low Rising Edge of Data Strobe Data Strobe Reference Clk Clk x2 Data Even 0 Data Stable Reference Clock High Rising Edge of Data Strobe Data Strobe Reference Clk Clk x2 Data Even 0 Data Stable Not stable MO/EAB/RTN/D Magnus Själander 2002-12-13 15
Synchronization of the Data Continued High D QI Clk I Phase S Q Simplified Phase Detector & High D QII R Clk II Clk I Clk II Q I Q II Phase Undefined Time Line Time Line Time Line MO/EAB/RTN/D Magnus Själander 2002-12-13 16
Floorplan 50 µ m AHB I Read, Write and Address Buss Data Buffer (AHB I) 155 µ m AHB I Control Signals 50 µ m DDR Control Clock Signals Signals 185 µ m 700 µ m DDR Memory Controller Address and APB Signals Data Buss 50 µ m AHB II Control Signals 155 µ m Data Buffer (AHB II) AHB II Read, Write and Address Buss 50 µ m 35 µ m 630 µ m 20 µ m 15 µ m 700 µ m AHB Interface region MO/EAB/RTN/D Magnus Själander 2002-12-13 17
Place & Route Data Buffer I ABH I Data Buffer II AHB II AHB Core Refresh RW command AHB x2 Initialization Command Timing APB Current Address Open Banks Top Arbiter Next Address Data Out MO/EAB/RTN/D Magnus Själander 2002-12-13 18
Future Work • Improved Refresh Handling • Attempt to Reduce Initial Latency for Bursts • Improved Buffer Handling MO/EAB/RTN/D Magnus Själander 2002-12-13 19
Conclusion • Working Implementation • Smaller Changes to Improve Performance • Highlights Difficulties and Solutions MO/EAB/RTN/D Magnus Själander 2002-12-13 20
Questions ? 2002-12-13
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