Constructing Circuits Using Wired Descriptions Kasyab P. - PowerPoint PPT Presentation

Constructing Circuits Using Wired Descriptions Kasyab P. Subramaniyan Department of Computer Science and Engineering Chalmers University of Technology kasyab@chalmers.se Page 1

Outline • Motivation and Background • Wired • Backend Flow • Case Studies • Future Work Page 2

Motivation • Transistor geometries growing smaller - density increasing  Moore’s Law • Designs becoming larger and more complex • Variability adversely affects circuits - affects yield • Methodologies to support design of large designs Page 3

Motivation • Custom layout – high NRE – requires special competence – fully utilizes performance of technology A half adder layout using ST 90nm technology Page 4

Motivation • Automatic place & route – low NRE – heuristics don’t guarantee efficient use of technology A Fully placed & routed 32-bit HPM Mulitplier using ST 90-nm library cells Page 5

Background • Tegola Structure Optimizer: http://www.tuscanyda.com • Intel Integrated Design & Verification (IDV): C. Seger , “Integrating Design and Verification - from Simple Idea to Practical System,” in Fourth ACM and IEEE Intl Conf. on Formal Methods and Models for Co-Design (MEMOCODE), 2006. • Work on data path circuits of fixed word length . Page 6

Wired • Developed by Emil Axelsson • More information : http://www.cs.chalmers.se/~emax/wired/index.html • Implemented using Haskell • Applicable to layouts that exhibit regularity Page 7

Wired • Covers three aspects of a circuit description - 1: – Logic function as technology mapped netlist myFunc (a,b,c) = do c’ < - ivsvtx2 c bc <- an2svtx2 (b,c ’) or2svtx2 (a,bc) Description of (A + B.C’) in Wired Page 8

Wired • Covers three aspects of a circuit description - 2: – Cell placement bitMultPlaced (a,bs) = rightwards $ mapM bitMult1 bs where bitMult1 b = downwards $ (nd2svtx2 >=> ivsvtx2) (a,b) Placement in Wired Page 9

Wired • Covers three aspects of a circuit description - 3: – Some aspects of the wiring (experimental) *Main> analyzeTiming (input >>= myFunc) Time 9.781e-11 Basic Wire Awareness in Wired Page 10

Wired • Logical simulation is also possible • Interactive development • As output, DEF files can be produced *Main> simulate myFunc (0,1,1) 0 *Main> simulate myFunc (0,1,0) 1 Logic Simulation in Wired Page 11

Backend Flow • RTL Compiler : RTL Circuit Description • Technology mapped to 90-nm GP-SVT ST Micro. • Parts integrated via Wired made black boxes. RTL Wired Compiler • Wired netlist integrated in SoC Encounter Input netlist DEF file Black Box Information • Backend flow completed to produce GDS II SoC Foundry Encounter Libs GDSII Page 12

Backend Flow Load Netlist • Import design with LEF files for the black boxes Floorplan & Partitions • Set up initial floorplan Block Development • Create physical hierarchies Integration • Specify & commit the partition(s) (black boxes) Place Route • Run a (non-timing driven) placement Verify • Save the partitions & unload design using `freeDesign` GDSII Page 13

Backend Flow Load Netlist Floorplan & Partitions • Load technology libraries Block Development • Use `loadDefFile` to load the Wired netlist Integration • Perform any additional placement tasks Place • Save (replace) the partition netlist Route Verify GDSII Page 14

Backend Flow • Run `updateBlock` Load Netlist Floorplan & Partitions • Adjust the floorplan Block Development • Run timing driven placement Integration • Set up the clock tree and synthesize it Place • Run routing for the entire design Route Verify • Ensure all DRC's are satisfied GDSII • Complete pre-Sign-Off checks Page 15

Case Studies • Previous work using only Wired descriptions. • Focused on purely combinational circuits - mainly prefix adders and multipliers M. Sheeran , “Generating Fast Multipliers Using Clever Circuits,” in 5th Intl Conf. on Formal Methods in Computer-Aided Design (FMCAD), ser. Lecture Notes in Computer Science, vol. 3312. Springer, 2004, pp.6 – 20. • These case studies focus on implementations • Multipliers: K. P. Subramaniyan, E. Axelsson, M. Sheeran, and P. Larsson-Edefors , “Layout Exploration of Geometrically Accurate Arithmetic Circuits,” in IEEE International Conference on Electronics, Circuits, and Systems, Dec. 2009. • Shifters: A. Bardizbanyan, K. P. Subramaniyan and P. Larsson-Edefors ,” Generation and Exploration of Layouts for Area- Efficient Barrel Shifters”, IEEE Computer Society Annual Symposium on VLSI, Jul. 2010 (Accepted for publication). Page 16

Case Studies - Multipliers • Commonly used in circuits • Two types of Parallel Multipliers:  Array Multipliers  Logarithmic Depth Multipliers • High Performance Multiplier (HPM): • Based on the log depth Dadda Multiplier • Exhibits regularity as well • Original layout triangular  Transformation to rectangular layout Page 17

Case Studies - Multipliers Page 18

Case Studies - Multipliers Page 19

Case Studies - Multipliers Page 20

Case Studies - Multipliers Triangular 32-Bit HPM Multiplier Page 21

Case Studies - Multipliers Triangular 32-Bit HPM Multiplier with Routing Channels Page 22

Case Studies - Multipliers Results : PPRT Geometry Switching Power (mW) Slack (ns) HPM Triangular 1.65 0.543 HPM Triangular 1.42 0.320 Channeled Comparison/Control Cases Dadda 1.32 0.992 Wallace 1.43 0.614 • Frequency for all designs limited to 250 MHz at 1.08V • Switching power determined by statistical switching of primary inputs Tool built into Encounter used for power analysis . • Page 23

Case Studies - Multipliers Congestion(1/2): Total Wire Length 200000 180000 160000 140000 RTL Flow 120000 Triangular 100000 Triangular 5ML 80000 Triangular RC 60000 40000 20000 0 RTL Flow Triangular Triangular Triangular RC 5ML Page 24

Case Studies - Multipliers Congestion(2/2): 60000 50000 40000 RTL Flow Triangular 30000 Triangular 5ML Triangular RC 20000 10000 0 M1 M2 M3 M4 M5 M6 M7 Page 25

Case Studies - Shifters • Shifters are vital components of the processors. • Most known example: • shift right by n bits  divide by 2 n • shift left by n bits  multiply by 2 n • Occupy large area & dissipate a lot of power. • Regular architectures  good candidates for the wired approach. • 8 bit, arithmetic and logic shift log 2 (8) = 3 levels 8x3 = 24 (2-to-1) mux Page 26

Case Studies - Shifters > renderWiredWithNets “circ” circ1 Page 27

Case Studies - Shifters Page 28

Case Studies - Shifters • Fanout is the most important problem for these kind of shifters. • Every select line drives input-size-times multiplexers. • Standard Cells have max fanout and max cap limits. • Check the correctness of the design in Soc Encounter: ‘ reportfanoutviolation ’ , ‘ reportcapviolation ’ • CORE90GPSVT_1.20V library is used for the evaluation and the comparison with the CAD tool. Page 29

Case Studies - Shifters Page 30

Case Studies - Shifters Page 31

Case Studies - Shifters Dimensions (um) Area(um 2 ) Slack time (ps) Power (mW) SoC 80.5 * 35.28 2827.16 FAIL FAIL 90 * 39 3510 43 5.588 85 * 43.12 3665,2 12 5.47 87*43.12 3751.44 54 5.587 90*43.12 3880,8 50 5.734 90*43.12 3880,8 52 5.545 Wired Dimensions (um) Area(um 2 ) Slack time (ps) Power (mW) 80.5 * 35.28 2827.16 28 4.08 82.7 * 35.28 2917,6 34 4.098 87.5 * 35.28 3087 36 4.47 92.3 * 35.28 3256,34 44 4.793 92.3 * 43.12 3256,34 46 4.769 101.4 * 35.28 3577,39 52 4.94 96.92 * 35.28 3419,33 54 4.876 Page 32

Future Work • Dense regular layouts lead to routing congestion • Routing channels added to layouts of regular circuits mitigates this somewhat. • What else can be done? • Custom characterized cells “Impact of Standard Cell Pin Placement on Routing Regularity of HPM Architectures”, Affaq Qamar, Kasyab P. Subramaniyan, and Per Larsson- Edefors, Swedish System on Chip Conference, May 2010. Page 33

Future Work A CO A CO CI CI B Z B Z B Z B Z CI CI A CO A CO A CO A CO CI CI B Z B Z B Z B Z CI CI A CO A CO Page 34

Future Work B S A CO HA HA A CO B S A CO A CO HA HA B S B S A B Z CO FA FA CI CI CO Z B A A CO A CO FA FA CI CI Z Z B B Page 35

Future Work Page 36

Future Work Page 37

Future Work Page 38

Future Work Page 39

Future Work Slack Total wire Avg. wire No. of (ns) length (µm) length (µm) Vias Flipped 0.185 208,938 52.0 24,352 Normal 0.259 230,058 57.3 39,784 ST. Lib. 0.804 165,783 41.3 41,110 NOTE: HA from custom library occupies the same area as the FA from ST library… Page 40

Future Work • Routing length decreases significantly • Number of Vias also decreases • Combine these observations to assess variability • Can this assessment be built into Wired? Page 41

Questions? Page 42