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Conflict Exceptions: Simplifying Concurrent Language Semantics with Precise Hardware Exceptions for Data-Races Brandon Lucia , Luis Ceze, Karin Strauss, Shaz Qadeer and Hans-J. Boehm Data-Races are Trouble Complicated language Usually

  1. Conflict Exceptions: Simplifying Concurrent Language Semantics with Precise Hardware Exceptions for Data-Races Brandon Lucia , Luis Ceze, Karin Strauss, Shaz Qadeer and Hans-J. Boehm

  2. Data-Races are Trouble Complicated language Usually incorrect, and specifications difficult to debug Negative impact on system reliability 2

  3. What If... Fail-Stop Semantics for Data-Races Semantics are Better data-race Safety: races can’t clear and simple debugging cause problems When a data-race occurs, throw an exception 3

  4. Requirements High-Performance - Always-on detection Precise detection - No false positives 4

  5. Prior Work Approx. Methods Happens-Before [Elmas’07, Flanagan‘09] [Savage’97, Zhou’07, Yu’05] ✓ ✗ Performance ✓ ✗ Precision 5

  6. Prior Work Approx. Methods Happens-Before [Elmas’07, Flanagan‘09] [Savage’97, Zhou’07, Yu’05] ✓ ✗ Performance ✓ ✗ Precision 5

  7. Prior Work Conflict Approx. Methods Happens-Before Exceptions [Elmas’07, Flanagan‘09] [Savage’97, Zhou’07, Yu’05] [ISCA ‘10] ✓ ✓ ✗ Performance ✓ ✓ ✗ Precision 5

  8. Conflict Exceptions Thread 1 Thread 2 Acquire(K) Rd Y Wr X Release(K) Rd T Wr T Acquire(M) Acquire(L) Rd X ... Rd Y ... Wr Y Wr Y Release(M) Release(L) 6

  9. Conflict Exceptions Thread 1 Thread 2 Acquire(K) Rd Y Wr X Release(K) Synchronization-Free Rd T Regions Wr T Acquire(M) Acquire(L) Rd X ... Rd Y ... Wr Y Wr Y Release(M) Release(L) 6

  10. Conflict Exceptions Thread 1 Thread 2 Acquire(K) Rd Y Wr X Release(K) Synchronization-Free Rd T Regions Wr T Acquire(M) Acquire(L) Rd X Conflict! ... Rd Y ... Wr Y Wr Y Release(M) Release(L) 6

  11. Conflict Exceptions Thread 1 Thread 2 Acquire(K) Rd Y Wr X Release(K) Synchronization-Free Rd T Regions Wr T Exception Acquire(M) Delivered Acquire(L) Rd X Conflict! ... Here Rd Y ... Wr Y Wr Y Release(M) Release(L) 6

  12. Conflict Exceptions Thread 1 Thread 2 Acquire(K) Rd Y Wr X U n d Release(K) e t e c t e Synchronization-Free d Rd T R a c Regions Wr T e Exception Acquire(M) Delivered Acquire(L) Rd X Conflict! ... Here Rd Y ... Wr Y Wr Y Release(M) Release(L) 6

  13. Conflict Exceptions Thread 1 Thread 2 Precisely detect only races that can effect consistency Acquire(K) Rd Y Wr X U n d Release(K) e t e Ignoring unimportant races is key to performance c t e Synchronization-Free d Rd T R a c Regions Wr T e Exception Acquire(M) Delivered Acquire(L) Rd X Conflict! ... Here Rd Y The Guarantee : ... Wr Y Exception-Thrown? There was a data-race. Wr Y Release(M) Release(L) Exception-Free? Sequential Consistency. 7

  14. Language Level Benefits Reordering in Exception-Free SFRs is legal executions are SC Acquire(K) Acq(K) Rd X Rd Y Acquire(K) ✓ Wr X Wr X Wr64_Low X Rel(K) Acq(K) Wr64_Hi X Release(K) Rd X Release(K) Granularity Wr X independence Rel(K) 8

  15. Language Level Benefits Race semantics Programming is are simpler the same pthread_lock(K) Rd Y Acq(K) Wr X Rd X Wr Q Wr Z Wr X ! Acq(L) pthread_unlock(K) Rd X Racy programs are well-behaved 9

  16. Debugging and Reliability Concurrent, conflicting All races have some SFRs throw exceptions exceptional schedule Acq(K) Rd X Wr X ! Acq(L) Rd X Exception Handling: Damage Control: Shut Log + Recover down buggy module 10

  17. System Support for Conflict Exceptions 11

  18. Hardware/Software Interface New Instructions: BeginRegion and EndRegion Synchronization Operations are Singleton Regions Exceptions Thrown Precisely Before Conflicting Instruction 12

  19. Hardware/Software Interface Acquire(K) New Instructions: BeginRegion and EndRegion BeginRegion Rd Y Wr X EndRegion Synchronization Operations are Singleton Regions Release(K) BeginRegion Exceptions Thrown Precisely Rd T Before Conflicting Instruction Wr T EndRegion 12

  20. Access Monitoring Byte-granular access information is required Line-level N-bit Supplied Bit Access Bits Local Read ... Local Write ... Remote Read Remote Write N-byte Cache Line Exception Test: compare appropriate local and remote bits 13

  21. Coherence Support CPU 1 CPU 2 Read Read Request Coherence Actions Local Remote Read V Write Write Reply Bits Bits CPU 1 CPU 2 Write Write/Invalidate Coherence Actions Local Local Invalidate Read Write Ack Bits Bits 14

  22. Coherence Support CPU 1 CPU 2 Read Read Request Coherence Actions Local Remote Read V Write Write Reply Bits Bits CPU 1 CPU 2 Write Write/Invalidate Coherence Actions Local Local Invalidate Read Write Ack Bits Bits 14

  23. Ending a Region End-Of-Region Message For all supplied lines... CPU 1 CPU 2 Address Local Write Local Read Bits Bits End-Of-Region Ack Ending a Region Clears Remote Bits Specified in EOR Msg 15

  24. Putting It Together CPU 1’s Cache CPU 2’s Cache Sup Sup A B C D A B C D LR LR LW LW RR RR RW RW A B C D A B C D CPU 1’s Code CPU 2’s Code BeginRegion BeginRegion Wr A Rd C EndRegion BeginRegion Wr C 16

  25. Putting It Together CPU 1’s Cache CPU 2’s Cache Sup Sup A B C D A B C D LR LR LW LW RR RR RW RW A B C D A B C D CPU 1’s Code CPU 2’s Code BeginRegion BeginRegion Wr A Rd C EndRegion BeginRegion Wr C 16

  26. Putting It Together CPU 1’s Cache CPU 2’s Cache Sup Sup A B C D A B C D LR LR LW LW RR RR RW RW A B C D A B C D CPU 1’s Code CPU 2’s Code BeginRegion BeginRegion Wr A Rd C EndRegion BeginRegion Wr C 16

  27. Putting It Together CPU 1’s Cache CPU 2’s Cache Sup Sup A B C D A B C D LR LR LW LW RR RR RW RW A B C D A B C D CPU 1’s Code CPU 2’s Code BeginRegion BeginRegion Wr A Rd C EndRegion BeginRegion Wr C 16

  28. Putting It Together CPU 1’s Cache CPU 2’s Cache Sup Sup A B C D A B C D LR LR LW LW RR RR RW RW A B C D A B C D CPU 1’s Code CPU 2’s Code BeginRegion BeginRegion Wr A Rd C EndRegion BeginRegion Wr C 16

  29. Putting It Together CPU 1’s Cache CPU 2’s Cache Sup Sup A B C D A B C D LR LR LW LW RR RR RW RW A B C D A B C D CPU 1’s Code CPU 2’s Code BeginRegion BeginRegion Wr A Rd C EndRegion BeginRegion Wr C 16

  30. Putting It Together CPU 1’s Cache CPU 2’s Cache Sup Sup A B C D A B C D LR LR Rd Req LW LW RR RR RW RW A B C D A B C D CPU 1’s Code CPU 2’s Code BeginRegion BeginRegion Wr A Rd C EndRegion BeginRegion Wr C 16

  31. Putting It Together CPU 1’s Cache CPU 2’s Cache Sup Sup A B C D A B C D LR LR LW LW RR RR RW RW A B C D A B C D CPU 1’s Code CPU 2’s Code BeginRegion BeginRegion Wr A Rd C EndRegion BeginRegion Wr C 16

  32. Putting It Together CPU 1’s Cache CPU 2’s Cache Sup Sup A B C D A B C D LR LR Rd Reply LW LW RR RR RW RW A B C D A B C D CPU 1’s Code CPU 2’s Code BeginRegion BeginRegion Wr A Rd C EndRegion BeginRegion Wr C 16

  33. Putting It Together CPU 1’s Cache CPU 2’s Cache Sup Sup A B C D A B C D LR LR LW LW RR RR RW RW A B C D A B C D CPU 1’s Code CPU 2’s Code BeginRegion BeginRegion Wr A Rd C EndRegion BeginRegion Wr C 16

  34. Putting It Together CPU 1’s Cache CPU 2’s Cache Sup Sup A B C D A B C D LR LR LW LW RR RR RW RW A B C D A B C D CPU 1’s Code CPU 2’s Code BeginRegion BeginRegion Wr A Rd C EndRegion BeginRegion Wr C 16

  35. Putting It Together CPU 1’s Cache CPU 2’s Cache Sup Sup A B C D A B C D LR LR EoR LW LW RR RR RW RW A B C D A B C D CPU 1’s Code CPU 2’s Code BeginRegion BeginRegion Wr A Rd C EndRegion BeginRegion Wr C 16

  36. Putting It Together CPU 1’s Cache CPU 2’s Cache Sup Sup A B C D A B C D LR LR LW LW RR RR RW RW A B C D A B C D CPU 1’s Code CPU 2’s Code BeginRegion BeginRegion Wr A Rd C EndRegion BeginRegion Wr C 16

  37. Putting It Together CPU 1’s Cache CPU 2’s Cache Sup Sup A B C D A B C D LR LR LW LW RR RR RW RW A B C D A B C D CPU 1’s Code CPU 2’s Code BeginRegion BeginRegion Wr A Rd C EndRegion BeginRegion Wr C 16

  38. Putting It Together CPU 1’s Cache CPU 2’s Cache Sup Sup A B C D A B C D LR LR LW LW RR RR RW RW A B C D A B C D CPU 1’s Code CPU 2’s Code BeginRegion BeginRegion Wr A Rd C EndRegion BeginRegion Wr C 16

  39. Putting It Together CPU 1’s Cache CPU 2’s Cache Sup Sup A B C D A B C D LR LR Invalidate LW LW RR RR RW RW A B C D A B C D CPU 1’s Code CPU 2’s Code BeginRegion BeginRegion Wr A Rd C EndRegion BeginRegion Wr C 16

  40. Putting It Together CPU 1’s Cache CPU 2’s Cache Sup Sup A B C D A B C D LR LR LW LW RR RR RW RW A B C D A B C D CPU 1’s Code CPU 2’s Code BeginRegion BeginRegion Wr A Rd C EndRegion BeginRegion Wr C 16

  41. Putting It Together CPU 1’s Cache CPU 2’s Cache Sup Sup A B C D A B C D LR LR Inv Ack LW LW RR RR RW RW A B C D A B C D CPU 1’s Code CPU 2’s Code BeginRegion BeginRegion Wr A Rd C EndRegion BeginRegion Wr C 16

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