What are Exceptions? Exceptions are rare events triggered by the - PowerPoint PPT Presentation

8.1 8.2 What are Exceptions? • Exceptions are rare events triggered by the hardware and forcing the processor to execute a software handler EE 457 Unit 8 – – – Exceptions • Similar to conditional branches/subroutine calls “What Happens When Things Go Wrong” – Utilize the hardware already in place for branches – Flush pipeline – Fetch from entry point of software exceptions handler 8.3 8.4 Exception Processing Exception Examples 1 • Exception = Example Stage Action – Asynchronous (non-programmed) control transfer I/O Device Interrupt WB Take ASAP • A peripheral device requires action from the CPU – Synchronous system call/trap (Interrupt I/O Driven) • Must save PC of offending instruction, program state, and any information Operating System Calls (“Traps”) [e.g. File Open] ____ Precise needed to return afterwards • Trap instruction causes processor to enter kernel mode • Restore upon return User Program System Exception Instruction Tracing and Breakpoints ID Precise Handler --------- • When TRAP Bit is set all instructions cause exceptions --------- --------- • Particular instructions are flagged for exceptions --------- --------- (debugging) --------- --------- --------- --------- --------- Arithmetic Exceptions EX Precise --------- --------- • Overflow or Divide-by-0 --------- --------- --------- --------- Return from exception

8.5 8.6 Exception Examples 2 System Calls/Traps Example Stage Action • A controlled-method for user application calling OS Page Faults _______ Precise services • Virtual memory access fault (no Page Table entry resident in memory) • Switches processor to “kernel” mode where certain Misaligned Memory Address ____ Abort privileges are enabled that we would not want • Address is not multiple of operand size Process Memory Protection Violations ____ Abort normal user apps to access • Address is out of bounds; RWX violation Process Undefined Instructions ____ Precise • Decode unit does not recognize opcode or other fields (Why not Instruction Tracing and Breakpoint x86 System Call (old DOS OS call) • Could be useful to extend the instruction set abort) Single-stepping & Breakpoint in x86 IN AH, 01H Hardware failure WB Take ASAP INT 20H // getchar() • Unrecoverable hardware error is detected; execution is PSW TF compromised Processor Trap Flag Power Failure WB Take ASAP Status Word • Power has fallen below a threshold; Trap to software to save as much state as possible 8.7 8.8 Exception Processing MIPS Coprocessor 0 Registers • Status Register • Save necessary state to be able to restart the process – Enables and disables the handling of exceptions/interrupts – Save ____of offending instruction – Controls user/kernel processor modes • Call an appropriate _______________ to deal with • Kernel mode allows access to certain regions of the address space and execution of certain instructions the error / interrupt / syscall • Cause Register: Indicates which exception/interrupt occurred – Handler identifies cause of exception and handles it _______________________ Register • – Indicates the address of the instruction causing the exception – May need to save more state – This is also the instruction we should return to after handling the exception • Restore state and return to offending application (or Coprocessor registers can be accessed via the ‘mtc0’ and ‘mfc0’ • kill it if recovery is impossible) instructions – mfc0 $gpr,$c0_reg # R[gpr] = C0[c0_reg] – mtc0 $gpr,$c0_reg # C0[c0_reg] = R[gpr]

8.9 8.10 Status Register Cause Register Code Cause • Register 12 in coprocessor 0 • Register 13 in coprocessor 0 0 Interrupt (HW) • Bit definitions 4, 5 Load (4), Store (5) • Bit definitions Address Error – IM[7:0] – Interrupt Mask – BD – Branch Delay 6, 7 Instruc. (6), Data (7) Bus • 1 = Ignore interrupt / 0 = Allow interrupt • The offending instruction was in the branch Error delay slot – UM – User Mode 8 Syscall • EPC points at the branch but it was EPC+4 • 1 = User mode / 0 = Kernel mode 9 Breakpoint that caused the exception – ERL/EXL = Exception/Error Level 10 Reserved Instruc. – PI[7:0] – Pending Interrupt • 1 = Already handling exception or error / 0 = Normal exec. 11 CoProc. Unusable • 1 = Interrupt Requested / 0 = No interrupt • If either bit is ‘1’ processor is also said to be in kernel mode requested 12 Arith. Overflow – IE = Interrupt Enable – Exception Code – Indicates cause of 13 Trap exception (see table) • 1 = Allow unmasked interrupts / 0 = Ignore all interrupts 15 Floating Point 31 15 8 4 2 1 0 31 15 8 7 6 2 1 0 Status Cause ERL IM7 IM6 IM5 IM4 IM3 IM2 IM1 IM0 EXL 0 0 0 UM 0 0 BD PI7 PI6 PI5 PI4 PI3 PI2 PI1 PI0 0 Exception Code 0 0 0000 0000 0000 0000 IE 000 0000 0000 0000 Register Register 8.11 8.12 EPC Register Problem of Calling a Handler • Exception PC holds the address of the offending • We can’t use explicit ‘jal’ instructions to call instruction exception handlers since we don’t – Can be used along with ‘Cause’ register to find and correct _____________ some error conditions • _______ instruction used to return from exception Many instructions could cause .text an error condition. Or a handler and back to execution point in original code MAIN: ---- hardware event like a keyboard ---- (unless handling the error means having the OS kill press could occur at any point in ---- the code. the process) ---- ---- – _______ Operation: PC = EPC jr $ra 31 0 EPC = Exception PC Address of instruction that generated the exception

8.13 8.14 Solution for Calling a Handler Handler Calling Methods • Since we don’t know when an exception will occur there must be a preset location where an exception handler should be Kernel 0xffffffff Kernel 0xffffffff Kernel 0xffffffff defined or some way of telling the processor in advance where Space Space Space our exception handlers will be located INT 2 Hand. x3 INT n Hand. 0x80000??? • Method 1: _______________________ for master handler INT 2 Hand. – Early MIPS architecture defines that the exception handler should be 0x80000300 x1 Handler 1 INT 1 Hand. 0x80000200 x2 INT 1 Hand. located at 0x8000_0180. Code there should then examine CAUSE register Exception Exception and then call appropriate handler routine 0x80000180 Handler 0x80000180 Handler addr x3 addr x2 • Method 2: _______________ (usually for interrupts) 0x80000000 0x80000000 0x80000000 addr x1 – Each interrupt handler at a different address based on interrupt number User User User (a.k.a. vector) (INT1 @ 0x80000200, INT2 @ 0x80000300) Space Space Space • Method 3: ___________________ 0x00000000 0x00000000 0x00000000 – Table in memory holding start address of exception handlers (i.e. Method 1 Method 2 Method 3 overflow exception handler pointer at 0x0004, FP exception handler pointer at 0x0008, etc.) 8.15 8.16 Precise Exceptions Why are Exceptions So Important? • Two conditions: • Exceptions are part of the ISA (Instruction Set Architecture) specification – Synchronized with an instruction • A particular instruction caused the exception • Any implementation of an ISA must comply with its • Not an interrupt or some kind of failure “Exception model” – Must resume execution after handler • Precise exception handling constrains what the architecture • Restart the instruction causing the exception after exception handler can do returns • Not an exception that will cause the process to abort – Exceptions are rare yet we must functionally support them – If we did not have to comply to the exception model architects would • Not difficult in a processor executing one instruction at a time have a lot more freedom in their design • Very difficult in architectures in which multiple instruction execute concurrently (i.e. our 5-stage pipeline) When designing micro-architectures for the common case, exceptions must always be in the back of your mind!