Configurations and Optimizations of TDMA Schedules for Periodic Packet Communication on Networks on Chip Tim Harde 1 , Matthias Freier 2 , uggen 1 , and Jian-Jia Chen 1 Georg von der Br¨ 1 TU Dortmund University, Germany 2 Robert Bosch GmbH, Germany 11.10.2018 von der Br¨ uggen (TU Dortmund) 1 / 19
Table of Content • Model and Design • Communication Tasks • Network on Chip • TDMA • TDMA Approach for a NoC • Greedy Heuristic • Rectangular Scheduling (Solver Based) • Evaluation • Conclusion von der Br¨ uggen (TU Dortmund) 2 / 19
Communication Tasks Periodic communication task τ i = ( T i , D i , P i , R i , r i , d i ) • period T i • relative deadline D i • packet size P i • route R i through the network • source node r i • destination node d i • infinite number of packets P i , j T i D i transmission time P i , 1 P i , 2 P i , 3 t 0 von der Br¨ uggen (TU Dortmund) 3 / 19
Communication Tasks Periodic communication task τ i = ( T i , D i , P i , R i , r i , d i ) • period T i • relative deadline D i , implicit deadline: D i = T i • packet size P i • route R i through the network • source node r i • destination node d i • infinite number of packets P i , j T i D i transmission time P i , 1 P i , 2 P i , 3 t 0 communication task set τ = { τ 1 , τ 2 , ..., τ n } • harmonic: ∀ τ i , τ j ∈ τ : if T i < T j then T j = a · T i , a ∈ N von der Br¨ uggen (TU Dortmund) 3 / 19
Network on Chip Architecture • r × s 2D-mesh • directed graph: C 0 , 2 C 1 , 2 C 2 , 2 • nodes: • cores C x , y S 0 , 2 S 1 , 2 S 2 , 2 • switches S x , y C 0 , 1 C 1 , 1 C 2 , 1 • edges: • links L node 1 S 0 , 1 S 1 , 1 S 2 , 1 node 2 C 0 , 0 C 1 , 0 C 2 , 0 S 0 , 0 S 1 , 0 S 2 , 0 von der Br¨ uggen (TU Dortmund) 4 / 19
Network on Chip Architecture • r × s 2D-mesh • directed graph: C 0 , 2 C 1 , 2 C 2 , 2 • nodes: • cores C x , y S 0 , 2 S 1 , 2 S 2 , 2 • switches S x , y C 0 , 1 C 1 , 1 C 2 , 1 • edges: • links L node 1 S 0 , 1 S 1 , 1 S 2 , 1 node 2 Packets and Flits C 0 , 0 C 1 , 0 C 2 , 0 • flow control units (flits): S 0 , 0 S 1 , 0 S 2 , 0 • atomic units of communication • maximum payload p max : 32 bits • packet P i , j : • segmented into flits if P i > p max von der Br¨ uggen (TU Dortmund) 4 / 19
Network-on-Chip Cores C x , y • execute computational tasks • exchange messages (packets) C 0 , 2 C 1 , 2 C 2 , 2 • components: S 0 , 2 S 1 , 2 S 2 , 2 • processing unit • memory C 0 , 1 C 1 , 1 C 2 , 1 • network interface (up-/downlink) S 0 , 1 S 1 , 1 S 2 , 1 C 0 , 0 C 1 , 0 C 2 , 0 S 0 , 0 S 1 , 0 S 2 , 0 von der Br¨ uggen (TU Dortmund) 5 / 19
Network-on-Chip Cores C x , y • execute computational tasks • exchange messages (packets) C 0 , 2 C 1 , 2 C 2 , 2 • components: S 0 , 2 S 1 , 2 S 2 , 2 • processing unit • memory C 0 , 1 C 1 , 1 C 2 , 1 • network interface (up-/downlink) S 0 , 1 S 1 , 1 S 2 , 1 Switches S x , y C 0 , 0 C 1 , 0 C 2 , 0 • forward flits through the NoC • components: S 0 , 0 S 1 , 0 S 2 , 0 • routing logic • arbiter • switching fabric von der Br¨ uggen (TU Dortmund) 5 / 19
Network-on-Chip Links L node 1 node 2 • unidirectional connection • flit forwarding C 0 , 2 C 1 , 2 C 2 , 2 • constant link latency l S 0 , 2 S 1 , 2 S 2 , 2 C 0 , 1 C 1 , 1 C 2 , 1 S 0 , 1 S 1 , 1 S 2 , 1 C 0 , 0 C 1 , 0 C 2 , 0 S 0 , 0 S 1 , 0 S 2 , 0 von der Br¨ uggen (TU Dortmund) 6 / 19
Network-on-Chip Links L node 1 node 2 • unidirectional connection • flit forwarding C 0 , 2 C 1 , 2 C 2 , 2 • constant link latency l S 0 , 2 S 1 , 2 S 2 , 2 Synchronicity C 0 , 1 C 1 , 1 C 2 , 1 • fully synchronous system • global clock for NIs and switches S 0 , 1 S 1 , 1 S 2 , 1 C 0 , 0 C 1 , 0 C 2 , 0 S 0 , 0 S 1 , 0 S 2 , 0 von der Br¨ uggen (TU Dortmund) 6 / 19
Network-on-Chip Links L node 1 node 2 • unidirectional connection • flit forwarding C 0 , 2 C 1 , 2 C 2 , 2 • constant link latency l S 0 , 2 S 1 , 2 S 2 , 2 Synchronicity C 0 , 1 C 1 , 1 C 2 , 1 • fully synchronous system • global clock for NIs and switches S 0 , 1 S 1 , 1 S 2 , 1 C 0 , 0 C 1 , 0 C 2 , 0 Routing • XY-Routing S 0 , 0 S 1 , 0 S 2 , 0 • deterministic (in-order delivery) • deadlock-free von der Br¨ uggen (TU Dortmund) 6 / 19
Network-on-Chip Links L node 1 node 2 • unidirectional connection • flit forwarding C 0 , 2 C 1 , 2 C 2 , 2 C 2 , 2 • constant link latency l S 0 , 2 S 1 , 2 S 2 , 2 Synchronicity C 0 , 1 C 0 , 1 C 1 , 1 C 2 , 1 • fully synchronous system • global clock for NIs and switches S 0 , 1 S 1 , 1 S 2 , 1 C 0 , 0 C 1 , 0 C 2 , 0 Routing • XY-Routing S 0 , 0 S 1 , 0 S 2 , 0 • deterministic (in-order delivery) • deadlock-free Example : communication task τ i with r i = C 0 , 1 and d i = C 2 , 2 von der Br¨ uggen (TU Dortmund) 6 / 19
Network-on-Chip Links L node 1 node 2 • unidirectional connection • flit forwarding C 0 , 2 C 1 , 2 C 2 , 2 C 2 , 2 • constant link latency l L i 5 S 0 , 2 S 1 , 2 S 2 , 2 Synchronicity C 0 , 1 C 0 , 1 C 1 , 1 C 2 , 1 L i L i 4 • fully synchronous system 1 L i L i 2 3 • global clock for NIs and switches S 0 , 1 S 1 , 1 S 2 , 1 C 0 , 0 C 1 , 0 C 2 , 0 Routing • XY-Routing S 0 , 0 S 1 , 0 S 2 , 0 • deterministic (in-order delivery) • deadlock-free Example : communication task τ i with r i = C 0 , 1 and d i = C 2 , 2 ⇒ route R i : L C 0 , 1 S 0 , 1 L S 0 , 1 S 1 , 1 L S 1 , 1 S 2 , 1 L S 2 , 1 S 2 , 2 L S 2 , 2 C 2 , 2 von der Br¨ uggen (TU Dortmund) 6 / 19
Time Division Multiple Access (TDMA) TDMA frame slot 1 slot 2 slot 3 ... slot n TDMA slot t Idea: partitioning the access time to a specific resource von der Br¨ uggen (TU Dortmund) 7 / 19
Time Division Multiple Access (TDMA) TDMA frame slot 1 slot 2 slot 3 ... slot n TDMA slot t Idea: partitioning the access time to a specific resource Advantages Disadvantages • bandwidth guarantees • global synchronization • isolation • global overhead • predictable timing behavior • tough design problem • good analyzability von der Br¨ uggen (TU Dortmund) 7 / 19
Time Division Multiple Access (TDMA) TDMA frame slot 1 slot 2 slot 3 ... slot n TDMA slot t Idea: partitioning the access time to a specific resource Advantages Disadvantages • bandwidth guarantees • global synchronization • isolation • global overhead • predictable timing behavior • tough design problem • good analyzability Problem: parameter selection: frame size, slot size and alignment von der Br¨ uggen (TU Dortmund) 7 / 19
Global TDMA Approach τ j τ i t L c 0 s i s j • synchronous execution of the TDMA schedule on all nodes • start and end of a TDMA slot can be defined arbitrarily ⇒ unused bandwidth possible von der Br¨ uggen (TU Dortmund) 8 / 19
Global TDMA Approach τ j τ i t L c 0 s i s j • synchronous execution of the TDMA schedule on all nodes • start and end of a TDMA slot can be defined arbitrarily ⇒ unused bandwidth possible TDMA Parameters • TDMA cycle length c ⇒ identical for all TDMA arbiters • TDMA slot length s i ⇒ sufficient bandwidth to forward the flits of τ i von der Br¨ uggen (TU Dortmund) 8 / 19
TDMA Slot Aligning τ i L i t 1 0 c s i τ i L i t 2 0 c s i l τ i L i t 3 0 c s i 2 · l von der Br¨ uggen (TU Dortmund) 9 / 19
TDMA Slot Aligning τ i L i t 1 0 c s i τ i L i t 2 0 c s i l τ i L i t 3 0 c s i 2 · l • align TDMA slots on consecutively traversed links ⇒ immediate forwarding of flits ⇒ no buffering required ⇒ no flow control mechanism required (bandwidth guarantee) ⇒ no contention from other packets (isolation property) von der Br¨ uggen (TU Dortmund) 9 / 19
TDMA Slot Aligning τ i L i t 1 0 c s i τ i L i t 2 0 c s i l τ i L i t 3 0 c s i 2 · l • align TDMA slots on consecutively traversed links ⇒ immediate forwarding of flits ⇒ no buffering required ⇒ no flow control mechanism required (bandwidth guarantee) ⇒ no contention from other packets (isolation property) TDMA slot assignment respecting the alignment property von der Br¨ uggen (TU Dortmund) 9 / 19
TDMA Parameter Selection - Cycle Length TDMA Cycle Length • identical for all TDMA arbiters in the NoC von der Br¨ uggen (TU Dortmund) 10 / 19
TDMA Parameter Selection - Cycle Length TDMA Cycle Length • identical for all TDMA arbiters in the NoC TDMA cycle length c ∈ { T 1 , T 2 , ..., T n } von der Br¨ uggen (TU Dortmund) 10 / 19
TDMA Parameter Selection - Cycle Length TDMA Cycle Length • identical for all TDMA arbiters in the NoC TDMA cycle length c ∈ { T 1 , T 2 , ..., T n } Harmonic Property of τ : ⇒ packets are released at the same offset of the TDMA cycle ⇒ identical response times for consecutive packet releases von der Br¨ uggen (TU Dortmund) 10 / 19
TDMA Parameter Selection - Cycle Length TDMA Cycle Length • identical for all TDMA arbiters in the NoC TDMA cycle length c ∈ { T 1 , T 2 , ..., T n } Harmonic Property of τ : ⇒ packets are released at the same offset of the TDMA cycle ⇒ identical response times for consecutive packet releases Fragmentation : • T i < c : integer number of packets releases per TDMA cycle • T i = c : one packet release per TDMA cycle • T i > c : one packet release every T i c TDMA cycles von der Br¨ uggen (TU Dortmund) 10 / 19
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