CS 230 – Introduction to Computers and Computer Systems Lecture 17 – Caching Continued CS 230 - Spring 2020 3-1
Cache Writing Strategy Store word loads blocks just like load word Then what does it do with new value? Write-through store word updates both cache and main memory Write-back – many updates in same block only update cache, mark block as dirty add dirty bit column to cache diagram 1 (dirty) if store word executed for this block, 0 (clean) if not update main memory when dirty block is evicted and set dirty bit back to 0 if the new block came from a load word CS 230 - Spring 2020 3-2
Associative Caches n -way set associative divide a cache with M cache-blocks into M/n sets each set contains n cache-blocks sets are contiguous addresses have cache-set instead of cache-block for address P we have cache-set Cs = (P/B)MOD(M/n) in binary it’s the next log 2 (M/n) bits adjacent to the “within the block bits” tag is T = P/(BM/n) which is remaining bits in binary when loading: check all tags in cache-set for a hit CS 230 - Spring 2020 3-3
Fully Associative and Direct Mapped Direct-mapped cache is 1-way set associative n = 1 no choice of where to put blocks Fully associative n-way set associative with n = B allow a given block to go in any cache entry requires all entries to be searched at once hardware comparator per entry (expensive) CS 230 - Spring 2020 3-4
Replacement Policy Where do we put loaded blocks? associative caches give us a choice n=1 (direct-mapped) has only one block per set no choice, just put it in the one spot n>1 fill any empty spots in order if no empty spots: evict least recently used block that was interacted with (hit or miss) the longest time ago CS 230 - Spring 2020 3-5
Example Assume 2-way set associative, M = 8, B = 2 bytes, 8-bit machine word, least-recently used eviction policy Cache-set Index Valid Dirty Tag Data 000 N N 00 001 N N 010 N N 01 011 N N 100 N N 10 101 N N 110 N N 11 111 N N CS 230 - Spring 2020 3-6
Example Instruction Address Binary addr Hit/miss Cache set lw 44 10 00101 10 0 Miss 10 Cache-set Index Valid Dirty Tag Data 000 N N 00 001 N N 010 N N 01 011 N N 100 Y N 00101 Mem[0010110X] 10 101 N N 110 N N 11 111 N N CS 230 - Spring 2020 3-7
Example Instruction Address Binary addr Hit/miss Cache set lw 68 10 01000 10 0 Miss 10 Cache-set Index Valid Dirty Tag Data 000 N N 00 001 N N 010 N N 01 011 N N 100 Y N 00101 Mem[0010110X] 10 101 Y N 01000 Mem[0100010X] 110 N N 11 111 N N CS 230 - Spring 2020 3-8
Example Instruction Address Binary addr Hit/miss Cache set sw 45 10 00101 10 1 Hit 10 Cache-set Index Valid Dirty Tag Data 000 N N 00 001 N N 010 N N 01 011 N N 100 Y Y 00101 Mem[0010110X] 10 101 Y N 01000 Mem[0100010X] 110 N N 11 111 N N CS 230 - Spring 2020 3-9
Example Instruction Address Binary addr Hit/miss Cache set sw 8 10 00001 00 0 Miss 00 Cache-set Index Valid Dirty Tag Data 000 Y Y 00001 Mem[0000100X] 00 001 N N 010 N N 01 011 N N 100 Y Y 00101 Mem[0010110X] 10 101 Y N 01000 Mem[0100010X] 110 N N 11 111 N N CS 230 - Spring 2020 3-10
Example Instruction Address Binary addr Hit/miss Cache set lw 12 10 00001 10 0 Miss 10 Cache-set Index Valid Dirty Tag Data 000 Y Y 00001 Mem[0000100X] 00 001 N N 010 N N 01 011 N N The block 100 Y Y 00101 Mem[0010110X] 10 that was 101 Y N 00001 Mem[0000110X] here 110 N N before got 11 evicted 111 N N CS 230 - Spring 2020 3-11
Try it Yourself Draw a cache diagram showing what the cache would look like after loading or storing the following addresses from/to memory. What is the hit chance of this cache for this access sequence? Assume 4-way assoc., M = 8, B = 4 bytes, 8-bit machine word. lw 0x08, lw 0x3E, lw 0x83, lw 0x0B, sw 0x22, lw 0x32, sw 0x18 CS 230 - Spring 2020 3-12
Try it Yourself Draw a cache diagram showing what the cache would look like after loading or storing the following addresses from/to memory. What is the hit chance of this cache for this access sequence? Assume 4-way assoc., M = 8, B = 4 bytes, 8-bit machine word. lw 0x08, lw 0x3E, lw 0x83, lw 0x0B, sw 0x22, lw 0x32, sw 0x18 Cache-set Index Valid Dirty Tag Data 000 N N 001 N N 0 010 N N 011 N N 100 N N 101 N N 1 110 N N 111 N N CS 230 - Spring 2020 3-13
Try it Yourself Draw a cache diagram showing what the cache would look like after loading or storing the following addresses from/to memory. What is the hit chance of this cache for this access sequence? Assume 4-way assoc., M = 8, B = 4 bytes, 8-bit machine word. lw 0x08, lw 0x3E, lw 0x83, lw 0x0B, sw 0x22, lw 0x32, sw 0x18 miss Cache-set Index Valid Dirty Tag Data 00001 0 00 tag set xx 000 N Y 00001 Mem[000010XX] 001 N N 0 010 N N 011 N N 100 N N 101 N N 1 110 N N 111 N N CS 230 - Spring 2020 3-14
Try it Yourself Draw a cache diagram showing what the cache would look like after loading or storing the following addresses from/to memory. What is the hit chance of this cache for this access sequence? Assume 4-way assoc., M = 8, B = 4 bytes, 8-bit machine word. lw 0x08, lw 0x3E, lw 0x83, lw 0x0B, sw 0x22, lw 0x32, sw 0x18 miss miss Cache-set Index Valid Dirty Tag Data 00111 1 10 tag set xx 000 Y N 00001 Mem[000010XX] 001 N N 0 010 N N 011 N N 100 N Y 00111 Mem[001111XX] 101 N N 1 110 N N 111 N N CS 230 - Spring 2020 3-15
Try it Yourself Draw a cache diagram showing what the cache would look like after loading or storing the following addresses from/to memory. What is the hit chance of this cache for this access sequence? Assume 4-way assoc., M = 8, B = 4 bytes, 8-bit machine word. lw 0x08, lw 0x3E, lw 0x83, lw 0x0B, sw 0x22, lw 0x32, sw 0x18 miss miss miss Cache-set Index Valid Dirty Tag Data 10000 0 11 tag set xx 000 Y N 00001 Mem[000010XX] 001 Y N 10000 Mem[100000XX] 0 010 N N 011 N N 100 Y N 00111 Mem[001111XX] 101 N N 1 110 N N 111 N N CS 230 - Spring 2020 3-16
Try it Yourself Draw a cache diagram showing what the cache would look like after loading or storing the following addresses from/to memory. What is the hit chance of this cache for this access sequence? Assume 4-way assoc., M = 8, B = 4 bytes, 8-bit machine word. lw 0x08, lw 0x3E, lw 0x83, lw 0x0B, sw 0x22, lw 0x32, sw 0x18 miss miss miss hit Cache-set Index Valid Dirty Tag Data 00001 0 11 tag set xx 000 Y N 00001 Mem[000010XX] 001 Y N 10000 Mem[100000XX] 0 010 N N 011 N N 100 Y N 00111 Mem[001111XX] 101 N N 1 110 N N 111 N N CS 230 - Spring 2020 3-17
Try it Yourself Draw a cache diagram showing what the cache would look like after loading or storing the following addresses from/to memory. What is the hit chance of this cache for this access sequence? Assume 4-way assoc., M = 8, B = 4 bytes, 8-bit machine word. lw 0x08, lw 0x3E, lw 0x83, lw 0x0B, sw 0x22, lw 0x32, sw 0x18 miss miss miss miss hit Cache-set Index Valid Dirty Tag Data 00100 0 10 tag set xx 000 Y N 00001 Mem[000010XX] 001 Y N 10000 Mem[100000XX] 0 010 Y Y 00100 Mem[001000XX] 011 N N 100 Y N 00111 Mem[001111XX] 101 N N 1 110 N N 111 N N CS 230 - Spring 2020 3-18
Try it Yourself Draw a cache diagram showing what the cache would look like after loading or storing the following addresses from/to memory. What is the hit chance of this cache for this access sequence? Assume 4-way assoc., M = 8, B = 4 bytes, 8-bit machine word. lw 0x08, lw 0x3E, lw 0x83, lw 0x0B, sw 0x22, lw 0x32, sw 0x18 miss miss miss miss miss hit Cache-set Index Valid Dirty Tag Data 00110 0 10 tag set xx 000 Y N 00001 Mem[000010XX] 001 Y N 10000 Mem[100000XX] 0 010 Y Y 00100 Mem[001000XX] 011 Y N 00110 Mem[001100XX] 100 Y N 00111 Mem[001111XX] 101 N N 1 110 N N 111 N N CS 230 - Spring 2020 3-19
Try it Yourself Draw a cache diagram showing what the cache would look like after loading or storing the following addresses from/to memory. What is the hit chance of this cache for this access sequence? Assume 4-way assoc., M = 8, B = 4 bytes, 8-bit machine word. lw 0x08, lw 0x3E, lw 0x83, lw 0x0B, sw 0x22, lw 0x32, sw 0x18 miss miss miss+evic miss miss miss hit Cache-set Index Valid Dirty Tag Data 00011 0 00 tag set xx 000 Y N 00001 Mem[000010XX] 001 Y Y 00011 Mem[000110XX] 0 010 Y Y 00100 Mem[001000XX] 011 Y N 00110 Mem[001100XX] 100 Y N 00111 Mem[001111XX] 101 N N 1 110 N N 111 N N CS 230 - Spring 2020 3-20
Try it Yourself Draw a cache diagram showing what the cache would look like after loading or storing the following addresses from/to memory. What is the hit chance of this cache for this access sequence? Assume 4-way assoc., M = 8, B = 4 bytes, 8-bit machine word. lw 0x08, lw 0x3E, lw 0x83, lw 0x0B, sw 0x22, lw 0x32, sw 0x18 miss miss miss+evic miss miss miss hit 7 accesses 1 hits 6 misses 1/7 = 0.143 10 hit chance CS 230 - Spring 2020 3-21
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