Collaboration: Collaboration: The Semiconductor Industrys The - PowerPoint PPT Presentation

Collaboration: Collaboration: The Semiconductor Industry’s The Semiconductor Industry’s Path to Survival and Growth Path to Survival and Growth Dr. Michael R. Polcari President and CEO SEMATECH 15 March 2005 3/17/2005 J:\ADMCTR\OCE\M_Polcari\ITPC 10-04 1

Outline Outline • Environment – Economic Challenges – Technology Challenges • Solutions – Innovation and Manufacturability through Collaboration • SEMATECH examples 3/17/2005 J:\ADMCTR\OCE\M_Polcari\ITPC 10-04 2

“The future “The future ain't what it ain't what it used to be…” used to be…” - Yogi Berra - Yogi Berra 3/17/2005 J:\ADMCTR\OCE\M_Polcari\ITPC 10-04 3

The Electronics Ecosystem The Electronics Ecosystem $36,356T Global GDP $1,240B Electronics $213B Semiconductors $52B Semi. Equipment $28B Materials 3/17/2005 2004 data (GDP from 2003) Sources: World Bank, World Semiconductor Trade Statistics, VLSI Research, SIA, SEMI J:\ADMCTR\OCE\M_Polcari\ITPC 10-04 4 2004 data (GDP from 2003) Sources: World Bank, World Semiconductor Trade Statistics, VLSI Research, SIA, SEMI

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Growth may slow, but will continue… Growth may slow, but will continue… Worldwide Semiconductor Market $B 300 250 ? 200 ? 150 100 50 0 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 7 7 7 7 7 7 7 7 8 8 8 8 8 8 8 8 8 8 9 9 9 9 9 9 9 9 9 9 0 0 0 0 0 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 Sources: Gartner Dataquest and SIA, February 2004 3/17/2005 J:\ADMCTR\OCE\M_Polcari\ITPC 10-04 6

Business Challenges Business Challenges The new economy for microelectronics The new economy for microelectronics • Affordability • Affordability – Increasing costs – Increasing costs • Capital • Capital • Manufacturing • Manufacturing • R&D • R&D • Manufacturability • Manufacturability – Fab and equipment – Fab and equipment productivity productivity 3/17/2005 J:\ADMCTR\OCE\M_Polcari\ITPC 10-04 7

Semiconductor Manufacturing Challenge Semiconductor Manufacturing Challenge Wafer Fab Cost Trend 4 $3.3 3 $2.4 Cost ($B) 2 $1.6 $1.0 1 $0.4 $0.2 $0.1 $0.05 0 1975 1980 1985 1990 1995 2000 2005E 2010E Source: IC Insights, Inc. Mclean Report, 2004 3/17/2005 J:\ADMCTR\OCE\M_Polcari\ITPC 10-04 8

Semiconductor R&D Challenge Semiconductor R&D Challenge Chip Making R&D Versus Revenues 1.E+06 1.E+05 (Worldwide in $M) 1.E+04 1.E+03 — Semiconductor Revenue — Semiconductor Revenue 1.E+02 — Total RD&E (Chip + Eq) — Total RD&E (Chip + Eq) 1.E+01 1.E+00 1960 1964 1968 1972 1976 1980 1984 1988 1992 1996 2000 2004 2008 2012 2016 2020 Source: VLSI Research Inc., 2004 3/17/2005 J:\ADMCTR\OCE\M_Polcari\ITPC 10-04 9

International Technology Roadmap International Technology Roadmap for Semiconductors for Semiconductors 350 1994 1994 250 1997 1997 180 1998/1999 1998/1999 130 2000 2000 100 2001 2001 70 2003/2004 2003/2004 50 35 22 1995 1997 1999 2001 2003 2005 2007 2009 2011 2013 2015 2017 3/17/2005 J:\ADMCTR\OCE\M_Polcari\ITPC 10-04 10

Technology Challenges Technology Challenges Innovation required Innovation required Still no known Still no known solutions solutions in many areas: in many areas: - Lithography - Lithography - Front End - Front End - Interconnect - Interconnect - Metrology - Metrology Source: ITRS 2004 3/17/2005 J:\ADMCTR\OCE\M_Polcari\ITPC 10-04 11

Future Transistors Future Transistors Non-classical CMOS will take us through next 15 years Non-classical CMOS will take us through next 15 years Many Approaches Many Approaches Sub 10 nm Beyond CMOS Already Demonstrated nMOS MOSFET pMOS FINFET SOI SOI Transistor on thin SOI Source: Bruce Doris (IBM) Transistor on thin SOI 3/17/2005 J:\ADMCTR\OCE\M_Polcari\ITPC 10-04 12

Future Patterning Future Patterning Immersion Immersion Traditional Traditional Projection optics Liquid Liquid recovery supply Wafer stage Immersion (Scanning motion) liquid Wafer EUV EUV 3/17/2005 J:\ADMCTR\OCE\M_Polcari\ITPC 10-04 13

Future Connectivity Future Connectivity 2009 � 2003-2008 k eff ~ 3.1-3.6 k eff ~ 2.7-3.0 k eff ~ 2.3-2.6 Projects Projects Cu Low k & Reliability Optically active Determine; Nanotubes Molecules Roadmap Future Timelines Connectivity Critical Needs Next Generation Interconnect Optical Interconnects SWCNT 3/17/2005 J:\ADMCTR\OCE\M_Polcari\ITPC 10-04 14

Future Metrology Future Metrology CD-SEM of the Future? Migration of TEM LENS Technology to SEM Tomorrow Today Top Down Top Down Image Image FE source FE source Secondary Electron Detector Aberration Correction Scanning coils Lens Secondary Electron Detector wafer Lens Scanning Sample Stage Coils Tilt Beam Wafer Lens for sidewall Sample Stage metrology 3/17/2005 J:\ADMCTR\OCE\M_Polcari\ITPC 10-04 15

Future Manufacturing Future Manufacturing Faster Cycle time On-line Specs & Tool Active ISMI Project Fabs for Hot Lots Maintenance Manuals & High Mix Future projects Predictive 100% Direct Transport Maintenance AMHS for Fast Cycle Time Wafer Level Tracking and Recipe/Parameter Changes Large Scale Efficient Spares Process Control Management Systems Manufacturing Execution Systems Equipment Engineering Equipment Rapid Capabilities (EEC) Control Systems Process SECS Control Line Recipes R2R FDC SPC Factory Scheduler Matching And Material Control Yield PCS e-Diag. EPT Equipment Data Equipment Acquisition (EDA) for Data Rich Standardized Data Pervasive Partner, Customer Remote EDA Goal Or Supplier Today 10 chambers Diagnostics 10 chambers 50 variables per 10 variables per chamber chamber 3 Hz rate each 10 Hz rate each 300 values per sec 10,000 values per sec 3/17/2005 J:\ADMCTR\OCE\M_Polcari\ITPC 10-04 16

The New Economy for Microelectronics The New Economy for Microelectronics • Slower growth of industry foreseen, compared to last 30 years • Escalating R&D, capital, and manufacturing costs – A new factory at 90nm technology on 300mm wafers has a capital cost of $2-3B – Rising technology R&D product cycle costs • Staggering technology challenges – 193 immersion/EUV, high/low-k, masks, 3D interconnect, 300mm/450mm • Changing business models in the industry – Foundries, fabless and fab-lite – New alliances and partnerships 3/17/2005 J:\ADMCTR\OCE\M_Polcari\ITPC 10-04 17

Collaboration at All Levels Collaboration at All Levels • Device manufacturers – Crolles cluster: Freescale, Philips, STMicro, TSMC – IBM cluster: AMD, IBM, Infineon, Samsung • Equipment and materials suppliers and device manufacturers – SEMATECH, Selete, individual companies • Universities – SRC/MARCO Focus Centers – SEMATECH AMRC programs • Governments – Texas Advanced Materials Center – Albany Nanotech – IMEC • Suppliers 3/17/2005 J:\ADMCTR\OCE\M_Polcari\ITPC 10-04 18

Innovation and Manufacturability Innovation and Manufacturability Two ways to sustain Moore’s Law Two ways to sustain Moore’s Law Reduce Wafers Opperating Tool set Cost ($) cost ( $ ) cost ( $ ) wafer OEE area (cm 2 ) cost ( $ ) Increase Tool set Good Wafer area (cm 2 ) cost ( $ ) Output M o o r e ' s Function wafer Law COO (Transistors/bits) Wafer Productivity Size Conversion Challenges transistors area (cm 2 ) Design Lithography Metrology Technology Front-End Process Interconnect Challenges 3/17/2005 J:\ADMCTR\OCE\M_Polcari\ITPC 10-04 19

SEMATECH SEMATECH Worldwide collaboration Worldwide collaboration 3/17/2005 J:\ADMCTR\OCE\M_Polcari\ITPC 10-04 20

SEMATECH: Focus on Innovation and SEMATECH: Focus on Innovation and Manufacturability Manufacturability • SEMATECH is the catalyst for accelerating the commercialization of technology innovations into manufacturing solutions • Accelerated commercialization of university research ( AMRC ) • Advanced technology innovations ( SEMATECH ) • Manufacturing productivity ( ISMI ) • World-class R&D processing & prototyping ( ATDF ) • Benefits of collaboration – Save money – Reduce risk – Accelerate development – Increase productivity

SEMATECH SEMATECH Accelerating the next technology revolution Accelerating the next technology revolution 3/17/2005 J:\ADMCTR\OCE\M_Polcari\ITPC 10-04 22

FOSTERING INNOVATION FOSTERING INNOVATION 3/17/2005 J:\ADMCTR\OCE\M_Polcari\ITPC 10-04 23

Advanced Gate Stack for 45nm Node Advanced Gate Stack for 45nm Node Fundamental Materials Understanding Fundamental Materials Understanding 97 98 99 00 01 02 03 04 05 06 07 Began high-k Hf based oxide Metal/ high-k I mplementation FEP-RC program with stack strategy identified Ta 2 O 5 ,TiO 2 , HfO2 Electrical test methods etc Metal electrode materials EOT~ 0.6nm 0.8nm 0.8nm Aggressive targets for µ ~ 65% 85% 90% HP 45nm node SEMATECH FEP/Advanced Gate Stack Program SRC/FEP-RC SRC/FEP-TC AMRC Suppliers Working with more than 40 universities, suppliers, and consortia 3/17/2005 J:\ADMCTR\OCE\M_Polcari\ITPC 10-04 24