CENG 4480 L10 Memory 3 Bei Yu Reference : Chapter 11 Memories - PowerPoint PPT Presentation

CENG 4480 L10 Memory 3 Bei Yu Reference : • Chapter 11 Memories • CMOS VLSI Design—A Circuits and Systems Perspective • by H.E.Weste and D.M.Harris 1

Memory Arrays Memory Arrays Content Addressable Memory Random Access Memory Serial Access Memory (CAM) Read/Write Memory Read Only Memory Shift Registers Queues (RAM) (ROM) (Volatile) (Nonvolatile) Serial In Parallel In First In Last In Static RAM Dynamic RAM Parallel Out Serial Out First Out First Out (SRAM) (DRAM) (SIPO) (PISO) (FIFO) (LIFO) Electrically Programmable Erasable Mask ROM Flash ROM Programmable Erasable ROM Programmable ROM (PROM) ROM (EPROM) (EEPROM) L10 Memory-3 2

Read-Only Memories Read-Only Memories are nonvolatile • – Retain their contents when power is removed Mask-programmed ROMs use one transistor per bit • – Presence or absence determines 1 or 0 L10 Memory-3 3

NOR ROM 4-word x 6-bit NOR-ROM • Word 0: 010101 – Selected word-line high Word 1: 011001 – Represented with dot diagram Word 2: 100101 Word 3: 101010 weak pseudo-nMOS A1 A0 pullups 2:4 DEC ROM Array Y5 Y4 Y3 Y2 Y1 Y0 Looks like 6 4-input pseudo-nMOS NORs L10 Memory-3 4

EX: NOR ROM • Draw 4-word 4-bit NOR-ROM structure and dot diagram Word 0: 0100 Word 1: 1001 Word 2: 0101 Word 3: 0000 weak pseudo-nMOS A1 A0 pullups 2:4 DEC ROM Array Y5 Y4 Y3 Y2 Y1 Y0 L10 Memory-3 5

NAND ROM 4-word x 4-bit NAND-ROM • – All word-lines high with exception of selected row L10 Memory-3 6

EX. NAND ROM • What’s it function? WL[0]=0: WL[1]=0: WL[2]=0: WL[3]=0: L10 Memory-3 7

NOR ROM v.s. NAND ROM weak • NOR ROM: pseudo-nMOS A1 A0 pullups (+) Faster • 2:4 DEC (-) Larger Area (VDD lines) • ROM Array Y5 Y4 Y3 Y2 Y1 Y0 • NAND ROM: (+) High density, small area • (-) Slower • delay grows quadratically with the number of series transistors discharging the bitline. L10 Memory-3 8

NOR ROM Array Layout* Unit cell is 12 x 8 λ (about 1/10 size of SRAM) • word3 word2 word1 word0 bit4 bit3 bit2 bit1 bit0 bit5 L10 Memory-3 9

Row Decoders* ROM row decoders must pitch-match with ROM • – Only a single track per word! A0 A1 A0 A1 A0 A0 A1 A1 word3 word2 word1 word0 L10 Memory-3 10

Complete ROM Layout* L10 Memory-3 11

PROMs and EPROMs* Programmable ROMs • – Build array with transistors at every site – Burn out fuses to disable unwanted transistors Electrically Programmable ROMs • – Use floating gate to turn off unwanted transistors – EPROM, EEPROM, Flash Source Gate Drain Polysilicon Floating Gate Thin Gate Oxide (SiO 2) n+ n+ p bulk Si L10 Memory-3 12

NOR / NAND Flash Memory* • NOR flash: Intel 1988 • NAND flash: Toshiba 1989 [Toshiba’08] • NOR: faster, more expensive • NAND: higher density L10 Memory-3 13

Building Logic with ROMs ROM as lookup table containing truth table • – n inputs, k outputs requires 2 n words x k bits – Changing function is easy – reprogram ROM Finite State Machine • – n inputs, k outputs, s bits of state – Build with 2 n+s x (k+s) bit ROM and (k+s) bit reg inputs inputs outputs n ROM Array n k k ROM 2 n wordlines DEC s s state k outputs L10 Memory-3 14

Example: RoboAnt L R Let’s build an Ant Sensors: Antennae (L,R) – 1 when in contact Actuators: Legs Forward step F Ten degree turns TL, TR Goal: make our ant smart enough to get out of a maze Strategy: keep right antenna on wall (RoboAnt adapted from MIT 6.004 2002 OpenCourseWare by Ward and Terman) L10 Memory-3 15

L10 Memory-3 16

Lost in space Action: go forward until we hit something • – Initial state L10 Memory-3 17

Bonk!!! Action: turn left (rotate counterclockwise) • – Until we don’t touch anymore L10 Memory-3 18

A little to the right Action: step forward and turn right a little • – Looking for wall L10 Memory-3 19

Then a little to the right • Action: step and turn left a little, until not touching L10 Memory-3 20

Whoops – a corner! • Action: step and turn right until hitting next wall L10 Memory-3 21

Simplification Merge equivalent states where possible • L10 Memory-3 22

State Transition Table Current state Inputs Next state Output values S 1:0 L R S 1:0 ’ TR TL F 00 0 0 00 0 0 1 00 1 X 01 0 0 1 Lost 00 0 1 01 0 0 1 01 1 X 01 0 1 0 RCCW 01 0 1 01 0 1 0 01 0 0 10 0 1 0 10 X 0 10 1 0 1 Wall1 10 X 1 11 1 0 1 11 1 X 01 0 1 1 Wall2 11 0 0 10 0 1 1 11 0 1 11 0 1 1 L10 Memory-3 23

ROM Implementation • 16-word x 5 bit ROM S 1 S 0 L R L, R TL, TR, F ROM 0000 0001 S' 1:0 0010 0011 S 1:0 0100 0101 4:16 DEC 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 S 1 ' S 0 ' TR'TL' F' L10 Memory-3 24

PLAs A Programmable Logic Array performs any function • in sum-of-products form. Literals : inputs & complements • Products / Minterms : AND of literals • Outputs : OR of Minterms • AND Plane OR Plane bc ac ab Minterms Example: Full Adder • abc abc abc s abc abc abc abc = + + + abc c ab bc ac = + + out a b c s c out Inputs Outputs L10 Memory-3 25

NOR-NOR PLAs • ANDs and ORs not very efficient in CMOS • Dynamic or Pseudo-nMOS NORs very efficient • Use DeMorgan’s Law to convert to all NORs AND Plane OR Plane AND Plane OR Plane bc bc ac ac ab ab abc abc abc abc abc abc abc abc a b c a b c s c s c out out L10 Memory-3 26

PLA Schematic & Layout AND Plane OR Plane bc ac ab abc abc abc abc a b c s c out L10 Memory-3 27

PLAs vs. ROMs The OR plane of the PLA is like the ROM array • The AND plane of the PLA is like the ROM decoder • PLAs are more flexible than ROMs • – No need to have 2 n rows for n inputs – Only generate the minterms that are needed – Take advantage of logic simplification L10 Memory-3 28

RoboAnt PLA* • Convert state transition table to logic • Karnaugh map S 1:0 L R S 1:0 ’ TR TL F 00 0 0 00 0 0 1 00 1 X 01 0 0 1 00 0 1 01 0 0 1 01 1 01 0 1 0 01 0 1 01 0 1 0 01 0 0 10 0 1 0 10 X 0 10 1 0 1 10 X 1 11 1 0 1 11 1 X 01 0 1 1 TR S S = 11 0 0 10 0 1 1 1 0 TL S 11 0 1 11 0 1 1 = 0 F S S = + 1 0 L10 Memory-3 29

EX. RoboAnt Dot Diagram* S 1' S S LS LRS = + + 1 0 1 0 S 0' R LS LS = + + 1 0 TR S S = 1 0 TL S = 0 F S S = + 1 0 L10 Memory-3 30

Memory Arrays* Memory Arrays Content Addressable Memory Random Access Memory Serial Access Memory (CAM) Read/Write Memory Read Only Memory Shift Registers Queues (RAM) (ROM) (Volatile) (Nonvolatile) Serial In Parallel In First In Last In Static RAM Dynamic RAM Parallel Out Serial Out First Out First Out (SRAM) (DRAM) (SIPO) (PISO) (FIFO) (LIFO) Electrically Programmable Erasable Mask ROM Flash ROM Programmable Erasable ROM Programmable ROM (PROM) ROM (EPROM) (EEPROM) L10 Memory-3 31

CAMs* Extension of ordinary memory (e.g. SRAM) • – Read and write memory as usual – Also match to see which words contain a key adr data/key read CAM match write L10 Memory-3 32

10T CAM Cell* Add four match transistors to 6T SRAM • – 56 x 43 λ unit cell bit bit_b word cell cell_b match L10 Memory-3 33

CAM Cell Operation* Read and write like ordinary SRAM • For matching: • CAM cell clk – Leave wordline low weak miss row decoder match0 address – Precharge matchlines match1 – Place key on bitlines match2 – Matchlines evaluate match3 read/write column circuitry Miss line • data – Pseudo-nMOS NOR of match lines – Goes high if no words match L10 Memory-3 34