CaSE: Cache-Assisted Secure Execution on ARM Processors N1 N1NG - PowerPoint PPT Presentation

CaSE: Cache-Assisted Secure Execution on ARM Processors N1 N1NG NG ZHA ZHANG , KUN SUN, WENJING LOU, TOM HOU

Talk Outline ü Motivation and Background – Why this work ? ü Threat Model – What are we defending against ? ü CaSE: Cache-Assisted Secure Execution – How does it work? ü CaSE highlight – Challenges ? ü Evaluation – How did we do ? ü Conclusion and future Work

Threat to Mobile devices

ARM TrustZone – Trusted Execution Environment (TEE) System Wide Protection Secure World Normal World ü Divides system resources into two worlds ü Normal World runs the content rich OS ü Secure World runs security critical services ü The protection of resources includes - processor, memory and IO devices

Many Products use ARM TrustZone

Smart Devices Going Mo Mobile

Hardware Attacks - Cold Boot Attack

Previous Works on Coldboot Defense TRESOR Sec 2011 – Register-based RAM-less AES encryption Copker NDSS 2014 – Cache-based RAM-less RSA encryption PixelVault CCS 2014 – GPU based RAM-less encryption Sentry ASPLOS 2015 – Cache-based RAM-less encryption Mimosa S&P 2015 – Transactional-based RAM-less encryption

Multi-vector Adversary

Introducing CaSE - Goals ü Defense against Multi-Vector adversary ü Physical memory disclosure attack – Cold boot ü Compromised rich OS ü Provide confidentiality and integrity to both the code and data of the binaries in TEE ü Confidentiality – Protects IP, secret code, sensitive data ü Integrity – Program behavior

Threat Model System On Chip (SoC) Processor Cache NonSecure Secure Cache Cache NonSecure Normal World Memory Secure Memory DRAM NonSecure Rich OS Secure OS

Case-Assisted Execution in Secure World System On Chip (SoC) Processor Cache 0101010110101101 1001 1101 Context Secure storage Packer 1101 0101 0101010110101101 NonSecure Normal World Memory Secure Memory DRAM Secure OS NonSecure Rich OS

Case-Assisted Execution in Normal World System On Chip (SoC) Processor Cache 0101010110101101 0101010110101101011010100 1001 0101 1101 1101 CaSE Context Secure Manager storage Packer 1101 0101 0101 1101 0101010110101101 0101010110101101011010100 Secure Memory NonSecure Normal World Memory DRAM NonSecure OS Secure Rich OS

Controlling the Cache ü Cache Locking is available through L2 cache lockdown CP15 coprocessor ü The granularity of locking is per cache way ü On Cortex-A8, which has 8 way total 256KB L2 unified cache

SoC-Bound Execution – Cache Locking

Self Modifying Program System On Chip (SoC) L1 Instruction Cache L1 Data Cache L2 Unified Cache

Self Modifying Program System On Chip (SoC) L1 Instruction L1 Data Cache Cache L2 Unified Cache

Feasibility of using Cache as Memory

Performance Impact to the Application

Performance Impact to the System

Conclusion ü A secure cache-assisted SoC-bound execution framework ü Provide confidentiality and integrity to sensitive code and data of applications ü Protect against both software attacks and cold boot attack. ü In the future, we would like to further study efficient method to provide OS support to the TEE.