Carbon Nanotube Interconnects? Carl V. Thompson 1,3 , Vladimir M. Stojanovic 2,4 , Fred Chen 2,4 and Gilbert D. Nessim 1,3 1 Materials Science and Engineering, 2 Electrical Engineering and Computer Science 3 Microsystems Technology Laboratory, 4 Research Laboratory of Electronics M.I.T. • Overview of structure, properties and growth. • Electronic properties. • CNTs in circuits. • The case for MWCNT vias.
Structure of Single-Wall CNTs (SWCNTs) 1/3 metallic if n and m are random then 2/3 non-metallic
Multi-Wall CNTs (MWCNTs) A.P. Graham et al (Infineon) Appl. Phys. A 80, 1141–1151 (2005) Each wall conducts independently: 1/3 metallic if n and m for a given shell is random then 2/3 non-metallic
CNT Properties Electrical: • Ballistic conduction over distances of order 1 micron (~10 -4 Ω ·cm). ‘Metals’ with low resistivities, Semiconductors with high mobilities • Conductivity a strong function of adsorbates or reactants. Mechanical: • High elastic modulus (high stiffness) (~1 to 5 TPa vs. ~0.2 for steel). • Very high tensile strength (~10 to 100 GPa vs. ~1 for steel). Thermal: • High room temperature thermal conductivity (~2000W/mK vs. ~400W/mK for copper). Electrical Stability: • Maximum current density ( 10 9 A/cm 2 vs. <10 7 A/cm 2 for Cu). Chemical Stability: • C binding energy in graphene ~12 eV vs. Cu at a Cu surface ~ 4eV
Growth of CNTS vapor-solid- tube Catalyst Formation: Uncontrolled dewetting of catalyst thin films. Chhowalla et al (Cambridge U), J.Appl. Phys. 90, 5315 (2001).
Fundamental Assembly Methods Grow - In - Place Grow - Then - Place • Chemically-directed • Field-directed • Mechanically-directed
CNT Contact: SWCNTs vs. MWCNTs Conductance measurements for SWCNT and MWCNTs are usually made by deposition of metal on top of horizontal tubes. More relevant measurements However, for MWCNTs are made for MWCNTs with only the outer wall is contacted metal contacts to all walls so only the conductivity of the - grow MWCNTs on metal; open outer wall is measured other end for ohmic contact.
Fujitsu Program: MWCNT Bundle-filled Vias Kondo, MRS • 2 μ m-diameter vias • Cu lines, CNT vias • Deposition temperatures ~500C with hot-filament CVD • CNT densities up to 9 x 10 11 cm -2 with Co nanoparticles on TiN/Ta/Cu Y. Awano, IEICE Trans. Electron. E89–C, 1499 (2006); AMC 2006
Equivalent Circuit Model for a SWCNT c Q K c Q M Q ES L M = magnetic impedance C ES = electrostatic capacitance C Q = quantum capacitance ~ 100aF/ μ m L K = kinetic impedance ~16nH/ μ m C Q ~ C ES L K >> L M P.J. Burke, IEEE Trans. on Nanotech. 1 , 129 (2002)
Equivalent Circuit Model for a SWCNT c Q K c Q M Q ES λ ⎛ + ⎞ = + ⎜ ⎟ R R 1 R Q C ⎝ ⎠ L R Q = quantum resistance h = Ω ~ 6 . 5 k 2 2 N e R C = contact resistance chan L = length N chan = number of channels λ = electron mean free path ~ 1 μ m = 2 when diameter < 6nm (h = Planck’s constant, e = electronic charge)
Bundles of Single-Wall CNTs in Trenches Factors Affecting Resistance: • radius r • spacing s • mean free path λ • length L • fraction metallic f met • contact resistance R C
Bundles of Single-Wall CNTs in Trenches R C + (R Q /2) R L R C + (R Q /2) 1 2 n N 1 1 f N tubes ⎛ + ⎞ ∑ L = ≈ met tubes f = + ⎜ ⎟ R R 1 2 R met R R R i Q C λ ⎝ ⎠ 1 i i # 2 ρ = ρ N tubes ~ hw 2 2 cm 3 s 1 ρ = = ⇒ ρ 14 2 r 0 . 5 nm ~ 7 x 10 cm max 2 2 3 r max
Bundles of Single-Wall CNTs in Trenches f met =.33 r = 0.5nm ρ = ρ max A. Naeemi and J.D. Meindl, IEEE Trans. on Electron Dev. 54, 26 (2007) SWCNT bundles ‘win’ when L > 1 μ m Issue: no one knows a way to fill trenches at anywhere near the maximum density.
SWCNT Bundles in Vias Factors Affecting Resistance: • radius r • density ρ (#/cm 2 ) • mean free path λ • length L • fraction metallic f met • contact resistance R C Results similar to trenches: for ρ = ρ max R C = 0 R via,SWCNT ~ R Cu when L > 1 μ m But ρ max = 7 x 10 14 cm 2 Fujitsu: ρ ~ 10 12 cm 2 (for r via = 2 μ m)
Multi-Wall CNT Vias One MWCNT per pore in an ordered porous alumina scaffold • one MWCNT per pore grown on metallic underlayer for multi-wall contact • CMP or ion milling to trim and open MWCNT • deposit metal on opened MWCNT for multi-wall contact Krishnan, Nguyen, Thompson, Choi, and Foo, Nanotechnology 16 , 841 (2005).
Resistance of Multi-Wall CNTs resistance of shell i with radius r s r o ⎛ + ⎞ L = + ⎜ ⎟ R R 1 2 R i Q C λ ⎝ ⎠ r i h 13 = = Ω R k Q 2 N 2 N e s ch ch = g ( r ) 2 r S < 1.5nm S N ch /shell = g(r S )* = + r S > 1.5nm g ( r ) 0 . 3672 r 1 . 275 S S s = shell spacing ~ 0.34nm − r r = o i r i = inner shell radius N shells s r o = outer shell radius ⎛ ⎞ N 1 1 shells ∑ ⎜ ⎟ = f metallic = metallic fraction f ⎜ ⎟ metallic R ⎝ R ⎠ 1 i *Naeemi and Meindl, IEEE Electron Device Letters 27 , 338 (2006)
Node Resistance 1.47k Ω MWCNT 22nm 2.25k Ω 16nm 16.7k Ω SWCNTs 22nm 25k Ω 16nm 0.11k Ω Cu 22nm 0.35k Ω 16nm f met = 0.33 L < λ R C = 5k Ω r i = r SWCNT = 0.5nm SWCNT: ρ = 1 x 10 12 cm 2
for ρ = ρ max R SWCNT,bundle < R MWCNT however, for ρ = 10 12 cm 2 R SWCNT,bundle > R MWCNT but R Cu < R MWCNT < R SWCNT So why use CNTs? • High reliability ( > 10 9 A/cm 2 ) • Chemically stable (no liner required) • Can fill high-aspect-ratio vias ( > 1000 to 1 in 10nm pores) Resistance isn’t everything.
A System Perspective Intel 386 Intel 486 Intel Pentium Chip design used to be constrained only by delay. Each process generation would result in larger and/or more complex designs with more transistors running faster.
System Constraints Today Intel Core 2 Duo AMD Quad Core Opteron • At advanced process nodes: Increased relative wire delay - can’t scale frequency Leakage � No Voltage Scaling � Increase in power density • Designers utilize parallelism to improve performance, but still limited by power constraint
System Constraints Tomorrow • Multiple cores require communication between cores
System Constraints Tomorrow uP uP uP uP • Multiple cores require communication between cores • To keep increasing performance…
System Constraints Tomorrow • Multiple cores require communication between cores • To keep increasing performance… we want to increase the number of smaller & more efficient cores • Increases burden on network - still power constrained
Modeling the Network • Each connection in the network can be modeled as an inverter driving a wire and a load, or some multiple of that for repeated wires. F. Chen, A. Joshi, V. Stojanovic ́ and A. Chandrakasan, Nanonets Symposium 07
C DRV = driver capacitance R DRV = driver resistance R W = wire resistance C W = wire capacitance C LOAD = load capacitance P = pitch S = spacing (within layer) H = interlevel spacing C C = fringing capacitance (coupling within layer) C P = plate capacitance (coupling between layers)
Re-Engineering the Wires Normalized Delay Contours 2 C W , normalized to nominal C W(Cu) at 22 nm 22nm node C W /C W(Cu 22nm node) L = 256 μ m Fanout = 1 Nominal 1.5 Cu case 2 1 1.5 0.4 1 0.6 0.8 0.5 0 0.5 1 1.5 2 2.5 R W , normalized to nominal R W(Cu) R W /R W(Cu 22nm node) Look at changing the interconnect stack and wire properties to improve performance and energy
Re-Engineering the Wires Normalized Delay Contours 2 C W , normalized to nominal C W(Cu) at 22 nm 22nm node C W /C W(Cu 22nm node) L = 256 μ m Fanout = 1 Nominal 1.5 Cu case 2 Lower Resistance 1 1.5 Lower Capacitance 0.4 1 0.6 0.8 0.5 0 0.5 1 1.5 2 2.5 R W , normalized to nominal R W(Cu) R W /R W(Cu 22nm node) Look at changing the interconnect stack and wire properties to improve • performance (delay, a function of both R and C)
Re-Engineering the Wires Normalized Delay Contours 2 C W , normalized to nominal C W(Cu) at 22 nm 22nm node C W /C W(Cu 22nm node) L = 256 μ m Fanout = 1 Nominal 1.5 Cu case 2 No change in Energy 1 1.5 Decreasing Energy 0.4 1 0.6 0.8 0.5 0 0.5 1 1.5 2 2.5 R W , normalized to nominal R W(Cu) R W /R W(Cu 22nm node) Look at changing the interconnect stack and wire properties to improve • performance (delay, a function of both R and C) • energy (primarily a function of C)
Re-Engineering the Wires Normalized Delay Contours 2 C W , normalized to nominal C W(Cu) at 22 nm 22nm node C W /C W(Cu 22nm node) L = 256 μ m Fanout = 1 Nominal 1.5 Cu case 2 1 1.5 0.4 1 0.6 0.8 0.5 0 0.5 1 1.5 2 2.5 R W , normalized to nominal R W(Cu) R W /R W(Cu 22nm node) Higher resistance can be traded for lower capacitance to achieve lower power with little or no performance cost.
MWCNT Vias take advantage of the ability to fill vias with arbitrarily high aspect ratios • to increase interlayer spacing to reduce interlayer coupling capacitance • to use ‘reverse scaling’; reduce line thicknesses to reduce fringing capacitance, without loss of performance
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