Analysis of the Effects of Single Event Transients on an SAR-ADC - PowerPoint PPT Presentation

Analysis of the Effects of Single Event Transients on an SAR-ADC based on Charge Redistribution Graduate Program – Department of Electrical Engineering Federal University of Rio Grande do Sul - UFRGS Alisson J. C. Lanot, Tiago R. Balen {alisson.lanot, tiago.balen}@ufrgs.br

Outline - Motivation; - Theoretical Background: - Charge Redistribution SAR ADCs - Single Event Effects - Transient Faults on Programmable Capacitor Arrays (PCAs) - Methodology; - Results; - Current research.

Motivation - Analog-to-Digital converters are frequently used on data acquisition systems. - Critical applications subject such converters to environmental interactions (e.g. radiation effects or electromagnetic interference)

Charge Redistribution SAR ADCs - Characteristics: - Low Power - Low Area - Medium Resolution - Good Speed - Present in several commercial SoC: - PSoC5 - SmartFusion - MSP430F6638 (Texas Instruments)

Charge Redistribution SAR ADCs - Stages of Conversion: - 1) Sample: - 2) Hold: Kugelstadt, T. (2000)

Charge Redistribution SAR ADCs - 3) Charge Redistribution Process: Kugelstadt, T. (2000)

Theoretical Background - Single Event Effects (SEE) - Occurs when a particle collides with the semiconductor, ionizing it. - The effects are technology-dependent. Sturesson, F. et al. (2009)

Theoretical Background - Single Event Transient: I(t) = I 0 (e - t / τ1 – e - t / τ2 ) Messenger, G.C. IEEE Transactions on Nuclear Science , Vol. NS-29, No. 6, December 1982 - Arises on reversely-biased PN junctions.

Theoretical Background - Transient Faults on Programmable Capacitor Arrays: - First addressed on Balen, T.R. et. al. 12th Latin American Test Workshop(2011). - A fault on an inverter of a transmission gate may cause a misbalance on the capacitor array. - Though a Charge Redistribution ADC uses a similar topology, it differs a little!

Methodology - Current sources attached to candidate nodes of the switches. (S7.. S0) - Worst-Case: - Amplitude: 2mA - Pulse Width: 700ps

Methodology - 130 nm process (Predictive Technology Model) - Design of an 8-bit charge redistribution SAR ADC - SPICE Model - Experimental Data - FERLET-CAVROIS, V. et al. IEEE Transactions on Nuclear Science , vol.53, no.6, pp.3242-3252 - NARASIMHAM, B. et al. IEEE Transactions on Nuclear Science , vol.54, no.6, pp.2506-2511. - Fault Injection - Messenger’s double exponential model

Methodology - Switches are modelled as transmission-gates based 2:1 MUX.

Results - Switch SB (common node switch): Voltage at the comparator input showing an error caused due the change of state on switch SB.

Results - Switch S7 (or other MSBs): Voltage at the comparator input showing an error caused due the change of state on switch S7.

Discussion - The effect is observed mainly on switches with small widths: - (W/L) n = 520nm/130nm (4/1) - A complete correction to the faults on the switches may be reached at: - (W/L) n = 39µm/130nm (300/1) - An SET observed on an LSB switch on an early stage of conversion won’t impact the conversion. - Switch SB – Irrecoverable failure. May be mitigated with redundancy.

Current Research - So, how does a SET on the switches may affect a ramp on the input?

Current Research - So, how does the sizing of the switches may affect on the single event transients? (W/L = 40/1).

Questions? Thank you! Alisson J. C. Lanot alisson.lanot@ufrgs.br Tiago R. Balen tiago.balen@ufrgs.br