International Collaboration Centre for Research and Development on Satellite Navigation Technology in South East Asia An ultra-low-cost antenna array frontend for GNSS application Thuan D. Nguyen, Vinh T. Tran Tung H. Ta, Letizia Lo Presti NAVIS Centre, Hanoi University of Science and Technology, Vietnam Australian Centre for Space Engineering Research, School of Electrical Engineering and Telecommunication, UNSW Politecnico di Torino, Italy IGNSS 2016
Outline • Motivation of design a low-cost antenna array frontend • Proposed design for a low-cost antenna array frontend • Problems and Solution in designing the low-cost frontend • Synchronizing the received data • Mitigating clock drift • Verification of the antenna array frontend • Phase offset among antenna elements • Carrier to noise ratio improvement • Conclusion and further works
Motivation of design a low-cost antenna array frontend • Threats to GNSS signals: • Jamming (prevent GNSS receivers track GNSS signals) • Spoofing (provide the false position to GNSS receivers) ⇒ Detect and locate the source of interference Counterfeit signal is much stronger than authentic signal Receiver/ Spoofer
Motivation of design a low-cost antenna array frontend Antenna array based technique is the most effective technique to detect and mitigate interference because it is able to: • Control the reception pattern of the array • Increase signal-to-noise ratio • Suppress interference • Determine the DOA of GNSS satellites and interference • 𝑡 𝑛 𝑢 = 𝑡 1 𝑢 − 𝜐 𝑛 = 𝑡 1 𝑢 − Δ𝜍 𝑛 𝑑 • Δ𝜍 𝑛 = 𝒒 𝑛 ⋅ 𝒃 𝑡 𝜄 , 𝜚 = 𝑌 𝑛 sin 𝜄 cos 𝜚 + 𝑍 𝑛 sin 𝜄 sin 𝜚 + 𝑎 𝑛 cos 𝜄
Overview of antenna array frontend for GNSS • Limitations of the existing antenna array frontend for GNSS: • Cumbersome • Costly • Difficult for expansion (synchronization is performed in hardware part) Difficult to deployment × BPF ADC Interleaving BPF × ADC samples × BPF ADC ~ ~
Proposed antenna array frontend • In our design, the synchronization block is carried out by our specialized algorithm × BPF ADC USB/Ethernet Synchronization × BPF ADC USB/Ethernet × BPF USB/Ethernet ADC USB Hub Master Element ~ ~ (Equipped TCXO) Slave Elements (Shared Master TCXO)
Problems and Solution in designing the low-cost frontend Synchronization Problem: Element signals are collected separately, they must be synchronized prior to use Solution: Element 1 Subframe X Due to the use of a common clock for ADC Element 2 Subframe X Time difference among Element 3 elements is a product of a Subframe X multiple of samples and the sampling period. Subframe X Element 4 The number of samples can be evaluated based on GNSS SDR 𝜐 1 𝜐 2 𝜐 3
Problems and Solution in designing the low-cost frontend Clock phase shift Problem: Regardless of the use of a common clock for all elements, the tuned frequency of Local Oscillator (LO) is slightly different in each element corrupt the phase offset completely. 4 the tracking output of SV 9 the tracking output of SV 9 x 10 1 8 Inphase Prompt 0.8 Quadrature Prompt 6 0.6 4 0.4 Quadrature Prompt 0.2 2 Amplitude 0 0 -0.2 -2 -0.4 -0.6 -4 -0.8 -6 -1 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 Inphase Prompt -8 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 Time (ms)
Problems and Solution in designing the low-cost frontend Clock phase shift Δ𝑔 = ∠ 𝐽𝑅 𝑛 ( 𝑙 ) − ∠ 𝐽𝑅 𝑛 𝑙 − 1 Solution: 2 𝜌𝑈 𝑒 0.18 Shift Frequency 0.16 0.14 0.12 0.1 Hz 0.08 0.06 0.04 0.02 0 -0.02 0 100 200 300 400 500 600 seconds
Problems and Solution in designing the low-cost frontend Clock phase shift Solution (continue): Represent the delay between RTL2832 Tracking this element dongle loop and the first GPS Simulator element RTL2832 Clock phase shift dongle mitigation carrier phase Scatter plot of SV 9 1 0.8 0.6 RTL2832 Clock phase shift dongle Normalized quadrature prompt mitigation 0.4 Carrier phase 0.2 0 Code & Carrier replica ~ -0.2 -0.4 TCXO -0.6 -0.8 -1 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 Normalized inphase prompt
Antenna Array Frontend Verification • Experiment setup schematic RTL2832 Tracking dongle loop GPS Simulator The phase RTL2832 Clock phase shift difference among dongle mitigation Carrier phase offset the elements should be the same for all RTL2832 Clock phase shift dongle mitigation Carrier phase offset satellites Code & Carrier replica ~ TCXO
Antenna Array Frontend Verification Achieved results: Phase offset between element 2 and element 1 Phase offset between element 3 and element 1 Tracking Output of Element 2 Tracking Output of Element 3 1.5 1.5 PRN 17 PRN 17 PRN 5 PRN 5 PRN 13 PRN 13 1 1 PRN 9 PRN 9 Normalized Q-channel amplitude Normalized Q-channel amplitude 0.5 0.5 0 0 -0.5 -0.5 -1 -1 -1.5 -1.5 -1.5 -1 -0.5 0 0.5 1 1.5 -1.5 -1 -0.5 0 0.5 1 1.5 Normalized I-channel amplitude Normalized I-channel amplitude
Antenna Array Frontend Verification Achieved result: The C/N0 increase when using antenna array: 48 46 44 dBHz 42 40 Element 1 Element 2 38 Element 3 Beamed signal 36 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 ms
Conclusion • The preliminary results are very promising for not only GNSS application but also the other field. • In the future, such antenna array frontend will be used to suppress interference, point to the source of the interference and spoofing to benchmark the performance of the frontend .
THA HANK Y YOU F FOR Y YOUR ATTENTION!!! !!!
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