An Asynchronous Fully Digital DLL for DDR SDRAM Data Recovery Jim - PowerPoint PPT Presentation

MANCHE ST ER 1824 The University of Manchester An Asynchronous Fully Digital DLL for DDR SDRAM Data Recovery Jim Garside et al. University of Manchester

MANCHE ST ER 1824 Contents The University of Manchester ❏ The problem ❏ Why ‘asynchronous’ ❏ Some asynchronous bits and pieces ❏ Dynamic switching and glitches ❏ Overall system ❏ Results ❏ Critique

MANCHE ST ER 1824 The Problem The University of Manchester SDRAM ❏ Recover data from Capture DDR SDRAM Data Sync. Strobe Delay Data Strobe Want: 1 ❏ Want a reliable on-chip delay of clock period - - - 4 ❏ Strobes arrive ‘unexpectedly’ at an arbitrary phase to the internal clock ❏ Did have a 2x clock from which the SDRAM clock was derived

MANCHE ST ER 1824 Existing solutions The University of Manchester ❏ Previous solutions existed ❏ Some (potentially) not as good ❍ e.g. using a fixed delay chain ❏ DLLs relied on (self) calibration before operation ❍ Not adapting dynamically to (e.g.) temperature changes ❏ Not readily available!

MANCHE ST ER 1824 Why ‘asynchronous’? The University of Manchester … especially when the system is so synchronous! We looked at the delay problem ourselves: ❍ in ignorance without preconceptions ❍ producing a matched delay seemed like something we knew how to do! ❍ actual delay control is not synchronous with the system clock – not too scary! The result was: ❍ a novel solution ❍ with some useful properties

MANCHE ST ER 1824 Delay line The University of Manchester C C C C L M R ❏ Delays not particularly remarkable ❏ Control adopted from Amulet2e ❍ arbitrarily extensible with three control signals

MANCHE ST ER 1824 Phase comparator The University of Manchester inc r0 mutex delay´ lock delay´ mutex r1 dec Operation: If one request is more than delay ′ ahead of the other it wins both mutexes. ❏ When the other request arrives an appropriate correction pulse results. If the requests arrive close to each other (within delay ′ ) lock is achieved. ❏ The (fixed) delays provide a window to prevent ‘hunting’.

MANCHE ST ER 1824 Asynchronous state machine The University of Manchester X A Y inc hold B dec Z incp C decp L master tristable slave tristable M R ❏ Modulo up/down counter converts pulses to rolling code

MANCHE ST ER 1824 Switching and glitching The University of Manchester ❏ Can the delay be adjusted (safely) whilst in use? 1.25 1.00 One stage later 0.75 Switched stage output V Two stages later 0.50 Control signal (before buffer) 0.25 0.00 100 ns ❏ SPICE simulation suggests so ❍ Plot shows worst glitch discovered ❏ Considerable ‘filtering’ provided by subsequent circuits

MANCHE ST ER 1824 Overall architecture The University of Manchester strobes in strobes out delay value trim control encoder delay individual lines trimming including delays spare arbiters phase detect async. reference FSM input test/control redundancy control test outputs ❏ One delay line is used for feedback to calibrate DLL ❏ Parallel delay lines are used to delay strobes ❏ Extra delay line provided for fault tolerance ❏ Other logic used for test and calibration

MANCHE ST ER 1824 Layout The University of Manchester ❏ Hand layout from standard cells ❏ 130 nm process ❏ 630 µ m × 25 µ m

MANCHE ST ER 1824 Test results The University of Manchester ❏ Measured from silicon 133 MHz SDRAM ‘max.’ speed 40 30 Stages employed ‘automatic’ DLL setting 20 Data not recovered 10 Data recovered 0 0 2 4 6 8 10 12 Clock period (ns) ❏ Wide window of tolerance ❏ Locks in the centre

MANCHE ST ER 1824 Potential improvements The University of Manchester Like most designs, by the time it’s made there are some new ideas ❏ Locking window ❍ There is a fixed time ‘window’ in the phase comparator ❍ This could be made programmable to reduce ‘hunting’ around a lock ❏ Power saving ❍ The manufactured DLL is continuously calibrated so a clock runs down one line all the time ❍ This is dumb! Physical conditions change slowly . Once locked the clock need only be sent ‘occasionally’ to confirm or re-establish a lock. ❍ It would be possible to ‘gate off’ edges from the ‘tail’ of the line They currently always run the full length

MANCHE ST ER 1824 Conclusions The University of Manchester ❏ The circuit works (well) in silicon ❍ Finds ‘best’ delay for required job ❍ Allows continuous calibration ❏ Fully digital solution: all standard cells ❍ (with the addition of a mutex) ❏ Asynchronous ‘mindset’ resulted in ‘unusual’ design ❍ Async. state machine used to solve S DRAM problem ❏ Several inefficiencies in manufactured circuit ❍ There were competing priorities at the time!

MANCHE ST ER 1824 Acknowledgements The University of Manchester ❏ Co-authors ❍ Steve Furber ❍ Steve Temple ❍ Dave Clark ❍ Luis Plana ❏ Rest of APT group ❏ Sponsors ❍ EPSRC ❍ ARM Ltd. ❍ Silistix