A Tail-feedback VCO with Self-Adjusting Current Modulation Scheme Aravind Tharayil Narayanan, Wei Deng, Kenichi Okada, and Akira Matsuzawa Tokyo Institute of Technology, Japan b. b. Matsuzawa Matsuzawa & Okada Lab. & Okada Lab. y y
Contents u Motivation u High Efficiency VCOs u Reliable Power-Efficient Solutions u Startup issue in Tail-Feedback VCO u Proposed VCO u Tail-Bias Vs Class-C u Measurement Results u Conclusion 2
Motivation 21.9% Others 9.1mW ref PD LPF VCO 32.5mW 76.1% Aim: N Low-power § VCO High-purity § Long lifetime § Ø Low-power VCO needed for longer battery-life [1] L. Vercesi, JSSC 2012. 3
High Efficiency VCOs VDD VDD LDO VDD V P V N V P V N K M V gbias V P V N VDD M1 M2 M1 M2 M1 M2 V Tail V Tail C Tail C Tail M3 M3 Class-C Class-D Class-F High voltage efficiency High current efficiency [3] L. Fanori, JSSC 2013. [2] P. Andreani, JSSC 2008. [4] M. Babaie, JSSC 2013. 4
High Efficiency VCOs – Contd. Excess Noise Factor 5 (ENF) u ENF = FoM MAX – FoM FoM MAX : Only depends on Q ENF : Only depends on topology 1 η I : Current efficiecny u ENF ∝ η I × η V η V : Voltage efficiecny ✗ High η V : § Loading effects § Reliability issues. ✓ High η I : § Good candidate for practical high efficiency VCO [5] M. Garampazzi, ESSCIRC 2014. 5
Class-C VCO V P V N VDD V DD V P V N V G,M1 V Tune V TH V gbias V G,M2 t I M1 I M2 I M1 I M2 M1 M2 I ω 0 ≈ I Bias I Tail V Tail C Tail ϖ 2 ϖ 3 ϖ 4 ϖ 0 t M3 Ø Impulse-shaped current for high efficiency [2] A. Mazzanti and P. Andreani, JSSC 2008. 6
Tail-Feedback VCO V P V N VDD V DD V P V N V G,M4 V TH V Tune V Tail V G,M3 t I M1 I M2 I M1 I M2 Φ C fb C fb M1 M2 I ω 0 ≈ I Bias V Tail V Tail ϖ 2 ϖ 3 ϖ 4 ϖ 0 t M3 M4 Ø High efficiency can be achieved if 𝚾 is small. [6] A. Musa, IEICE 2013. 7
Startup Issue Ø Large oscillation amplitude for better phase noise Phase Noise Improvment (dB) V DS 5 V DD 4 V TH 3 V Tail V T,eff 2 t 1 I ω 0 ≈ I Bias 0 0 30 60 90 I DS Conduction Angle (degrees) t - ϖ ϖ 0 Ø VCO fails to startup at low tail-bias voltage. 8
Proposed VCO VDD V Bias V P V N V Tune VDD C fb C fb VDD I M1 I M2 I B1 I B2 R b R b M1 M2 V b C b C b M5 M6 M3 M4 Bias Circuit 9
Self-Adjusting Tail-Current Modulation Ø Ensures robust startup 10
Self-Adjusting Tail-Current Modulation Ø Optimizes ‘ 𝚾 ’ for better phase noise 11
Contents u Motivation u High Efficiency VCOs u Reliable Power-Efficient Solutions u Startup issue in Tail-Feedback VCO u Proposed VCO u Tail-Bias Vs Class-C u Measurement Results u Conclusion 12
Efficiency and MOS Sizing in Class-C V DS ! !"# = ! !! − ( ! !" − ! !" ) V DD ! V TH -100 V GS Phase Noise [dBc/Hz] I max1 -105 −Φ 1 Φ 1 I DS1 Small MOS -110 I max2 −Φ 2 −Φ 2 -115 I DS2 -0.3 0.0 0.3 0.6 - ϖ - ϖ 0 ϖ ϖ 2 Large MOS 2 V gbias [V] Ø Large MOS required for better efficiency (class-C) [2] A. Mazzanti and P. Andreani, JSSC 2008. 13
Tail Noise Factor: Fixed Tail Bias V Tail i DS +i N V TH 0 i N ISF V Tail I DS Noise ϖ 2 ϖ 3 ϖ 4 ϖ Fixed Tail Bias 0 Ø Continuous Tail-Noise Up-Conversion in Class-C [7] S.L.J. Geirkink, JSSC 1999. 14
Tail Noise Factor: Modulated Tail Bias V T,eff i DS +i N V TH V T,eff =(V Tail +V mod ) V Tail i N V mod ISF V Tail I DS Noise ϖ 2 ϖ 3 ϖ 4 ϖ Modulated Tail Bias 0 Ø Reduced Tail-Noise Up-Conversion [7] S.L.J. Geirkink, JSSC 1999. 15
In Brief Tail-feedback VCO compared to class-C VCO Ø Better tuning range. Ø Similar if not better noise performance. Ø Start-up issue is solvable. 16
Contents u Motivation u High Efficiency VCOs u Reliable Power-Efficient Solutions u Startup issue in Tail-Feedback VCO u Proposed VCO u Tail-Bias Vs Class-C u Measurement Results u Conclusion 17
Measurement Technology 180nm CMOS F OSC 4.6GHz 530 𝛎 M PN@1MHz -119dBc/Hz Power 6.8mW FoM -184dBc/Hz 245 𝛎 M 18
Measurement -20 -40 Phase noise (dBc/Hz) -60 -80 -100 -120 -140 1K 10K 100K 1M 10M Offset Frequency (Hz) 19
Conclusion u VCO topologies for high-efficiency is briefly analyzed. u Current-efficient topology is identified as a viable candidate for practical design. u Tail-feedback VCO is capable of achieving similar if not better performance compared to class-C VCO. u The start-up issues present in tail-feedback VCO is briefly discussed. u A bias mechanism is presented for solving startup issues. u A VCO is implemented in 180nm CMOS process incorporating the proposed bias scheme. 20
APPENDIX 21
Analysis: Class-C VCO VDD VDD VP C L L C Cgs,m1 Cgd,m1 L C Cgd,m1 Cdc VP M1 Cgd,m3 Cgs,m1 C L Cgs,m3 CT Cgd,m3 M3 M3 VTail C T Cgs,m3 Conventioanl Class-C equivalent circuit Ø C GS has prominent effect on tank impedance 22
Analysis: Tail-Feedback VCO VDD VDD VP C L L C Cgd,m1 L C Cfb Cgs,m1 Cgd,m1 Cgd,m3 VP M1 Cgs,m1 Cfb C L Cgd,m3 Cgs,m3 VTail M3 Cgs,m3 Tail bias equivalent circuit Ø Cross-couple size is independent of ‘ 𝚾 ’ 23
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