a
play

a LOW POWER, LOW VOLTAGE ADC DESIGN ISSUES I Typical Supply - PowerPoint PPT Presentation

Dec 14, 2023 •7 likes •407 views

PRACTICAL DESIGN TECHNIQUES FOR SENSOR SIGNAL CONDITIONING 1 Introduction 2 Bridge Circuits 3 Amplifiers for Signal Conditioning 4 Strain, Force, Pressure, and Flow Measurements 5 High Impedance Sensors 6 Position and Motion Sensors 7

  1. PRACTICAL DESIGN TECHNIQUES FOR SENSOR SIGNAL CONDITIONING 1 Introduction 2 Bridge Circuits 3 Amplifiers for Signal Conditioning 4 Strain, Force, Pressure, and Flow Measurements 5 High Impedance Sensors 6 Position and Motion Sensors 7 Temperature Sensors I 8 ADCs for Signal Conditioning 9 Smart Sensors 10 Hardware Design Techniques 8.0 a

  2. LOW POWER, LOW VOLTAGE ADC DESIGN ISSUES I Typical Supply Voltages: ± 5V, +5V, +5/+3V, +3V I Lower Signal Swings Increase Sensitivity to All Types of Noise (Device, Power Supply, Logic, etc.) I Device Noise Increases at Low Currents I Common Mode Input Voltage Restrictions I Input Buffer Amplifier Selection Critical I Auto-Calibration Modes Desirable at High Resolutions 8.1 a

  3. ADCs FOR SIGNAL CONDITIONING I Successive Approximation N Resolutions to 16-bits N Minimal Throughput Delay Time N Used in Multiplexed Data Acquisition Systems I Sigma-Delta N Resolutions to 24-bits N Excellent Differential Linearity N Internal Digital Filter, Excellent AC Line Rejection N Long Throughput Delay Time N Difficult to Multiplex Inputs Due to Digital Filter Settling Time I High Speed Architectures: N Flash Converter N Subranging or Pipelined 8.2 a

  4. SUCCESSIVE APPROXIMATION ADC CONVERT START TIMING ANALOG COMPARATOR INPUT EOC, SHA DRDY, OR BUSY SUCCESSIVE APPROXIMATION REGISTER (SAR) DAC OUTPUT 8.3 a

  5. 3-BIT SWITCHED CAPACITOR DAC S C BIT1 BIT2 BIT3 (MSB) (LSB) _ A C TOTAL = 2C C C/ 2 C/ 4 C/ 4 + S1 S2 S3 S4 A IN S IN V REF SWITCHES SHOWN IN TRACK (SAMPLE) MODE 8.4 a

  6. RESOLUTION / CONVERSION TIME COMPARASION FOR REPRESENTATIVE SINGLE-SUPPLY SAR ADCs RESOLUTION SAMPLING POWER CHANNELS RATE 12-BITS 1.5MSPS 9mW 1 AD7472 12-BITS 500kSPS 85mW 8 AD7891 200kSPS 20mW AD7858/59 12-BITS 8 125kSPS 3.5mW 12-BITS 8 AD7887/88 14-BITS 285kSPS 60mW 8 AD7856/57 16-BITS 200kSPS 120mW 4 AD974 1MSPS 250mW AD7670 16-BITS 1 8.5 a

  7. TYPICAL SAR ADC TIMING SAMPLE X SAMPLE X+1 SAMPLE X+2 CONVST CONVERSION CONVERSION TRACK/ TRACK/ TIME TIME ACQUIRE ACQUIRE EOC, BUSY OUTPUT DATA DATA DATA X+1 X 8.6 a

  8. 12-BIT TWO-STAGE PIPELINED ADC ARCHITECTURE ANALOG SHA SHA INPUT + 1 2 _ SAMPLING CLOCK 6-BIT 6-BIT 7-BIT TIMING ADC DAC ADC 6 BUFFER REGISTER 7 6 ERROR CORRECTION LOGIC 12 OUTPUT REGISTERS OUTPUT DATA 12 8.7 a

  9. TYPICAL PIPELINED ADC TIMING SAMPLE X SAMPLE X+1 SAMPLE X+2 SAMPLING CLOCK OUTPUT DATA DATA DATA DATA X–2 X–1 X ABOVE SHOWS TWO CLOCK-CYCLES PIPELINE DELAY 8.8 a

  10. DRIVING SWITCHED CAPACITOR INPUTS OF AD7858/59 12-BIT, 200kSPS ADC +3V TO +5V 0.1µF 10k Ω Ω CUTOFF V IN 10k Ω Ω = 320kHz AV DD DV DD 0.1µF _ 50 Ω Ω 125 Ω Ω V IN : 0V TO +2.5V AD7858/59 AD820 AIN+ : +2.6V TO +0.1V AIN+ T 10nF 20pF + CAP DAC 125 Ω Ω 412 Ω Ω +100mV H + 0.1µF AIN– 10k Ω Ω 0.1µF _ V CM = +1.30V V REF H T T = TRACK +2.5V 10k Ω Ω H = HOLD 10.7k Ω Ω DGND AGND 0.1µF NOTE: ONLY ONE INPUT SHOWN 8.9 a

  11. DRIVING SINGLE-SUPPLY ADCs WITH SCALED INPUTS +5V +2.5V AD7890-10 REFERENCE 12-BITS, 8-CHANNEL 2k Ω Ω REFOUT/ + +2.5V TO ADC REF CIRCUITS REFIN _ R2 R S 7.5k Ω Ω V INX R1 TO MUX, SHA, ETC. ±10V 30k Ω Ω 0V TO +2.5V R3 ~ 10k Ω Ω V S AGND R1, R2, R3 ARE RATIO-TRIMMED THIN FILM RESISTORS 8.10 a

  12. BASIC CMOS ANALOG SWITCH +V S +V S ON P-CH –V S OFF V IN V OUT P-CH N-CH N-CH –V S R ON PMOS NMOS CMOS – SIGNAL VOLTAGE + 8.11 a

  13. SIMPLIFIED DIAGRAM OF A TYPICAL ANALOG MULTIPLEXER CHANNEL ADDRESS ADDRESS CLOCK REGISTER ADDRESS DECODER BUFFER, R ON SHA, CHANNEL 1 OR PGA R L R ON CHANNEL M 8.12 a

  14. WHAT'S NEW IN DISCRETE SWITCHES / MUXES? I ADG508F, ADG509F, ADG527F: ±15V Specified N R ON < 300 Ω Ω N Switching Time < 250ns N Fault Protection on Inputs and Outputs (–40V to + 55V) I ADG451, ADG452, ADG453: ±15V, +12V, ±5V Specified N R ON < 5 Ω Ω N Switching Time < 180ns N 2kV ESD Protection I ADG7XX-Family: Single-Supply, +1.8V to +5.5V N R ON < 5 Ω Ω , R ON Flatness < 2 Ω Ω N Switching Time < 20ns 8.13 a

  15. MULTIPLEXED SAR ADC FILTERING AND TIMING f s CHANGE f s / 2M CONVST, f s CHANNEL LPF 1 AIN 1 EOC, BUSY MUX LPF C SHA ADC DATA LPF M AIN M f c SEE TEXT CONVST TRACK/ TRACK/ CONVERT CONVERT ACQUIRE ACQUIRE EOC, BUSY MUX MUX SETTLING MUX SETTLING OUTPUT CHANGE CHANGE CHANGE CHANNEL CHANNEL CHANNEL 8.14 a

  16. SINGLE-POLE FILTER SETTLING TIME TO REQUIRED ACCURACY RESOLUTION LSB (%FS) # OF TIME f c /f s # OF BITS CONSTANTS, n 6 1.563 4.16 0.67 8 0.391 5.55 0.89 10 0.0977 6.93 1.11 12 0.0244 8.32 1.32 14 0.0061 9.70 1.55 16 0.00153 11.09 1.77 18 0.00038 12.48 2.00 20 0.000095 13.86 2.22 22 0.000024 15.25 2.44 f s = ADC Sampling Frequency f c = Cutoff Frequency of LPF C 8.15 a

  17. AD7858 12-BIT, 200kSPS 8-CHANNEL SINGLE-SUPPLY ADC DV DD AD7858/ AIN1 AD7858L T/H MUX AV DD AIN8 AGND 2.5V REF DGND REF IN / BUF REF OUT SWITCHED CREF1 CLKIN CAPACITOR DAC CONVST CREF2 SAR + ADC CONTROL BUSY CALIBRATION CAL MEMORY AND SLEEP CONTROLLER SERIAL INTERFACE/CONTROL REGISTER DIN DOUT SCLK 8.16 SYNC a

  18. AD7858 / AD7858L DATA ACQUISITION ADCs KEY SPECIFICATIONS I 12-Bit, 8Channel, 200kSPS (AD7858), 100kSPS (AD7858L) I System and Self-Calibration with Autocalibration on Power-Up I Automatic Power Down After Conversion (25µW) I Low Power: N AD7858: 15mW (V DD = +3V) N AD7858L: 5.5mW (V DD = +3V) I Flexible Serial Interface: 8051 / SPI / QSPI / µP Compatible I 24-Pin DIP, SOIC, SSOP Packages I AD7859, AD7859L: Parallel Output Devices, Similar Specifications 8.17 a

  19. SIGMA-DELTA ADCs I Low Cost, High Resolution (to 24-bits) Excellent DNL, I Low Power, but Limited Bandwidth I Key Concepts are Simple, but Math is Complex N Oversampling N Quantization Noise Shaping N Digital Filtering N Decimation I Ideal for Sensor Signal Conditioning N High Resolution N Self, System, and Auto Calibration Modes 8.18 a

  20. OVERSAMPLING, DIGITAL FILTERING, NOISE SHAPING, AND DECIMATION A f s QUANTIZATION Nyquist NOISE = q / 12 Operation q = 1 LSB ADC f s Oversampling f s 2 + Digital Filter B Kf s f s + Decimation DIGITAL FILTER DIGITAL ADC DEC REMOVED NOISE FILTER f s Kf s Kf s Oversampling 2 2 + Noise Shaping + Digital Filter C + Decimation Kf s f s REMOVED NOISE Σ∆ Σ∆ DIGITAL DEC MOD FILTER Kf s f s Kf s 2 2 8.19 a

  21. FIRST-ORDER SIGMA-DELTA ADC CLOCK f s INTEGRATOR Kf s V IN A ∫ + N-BITS ∑ DIGITAL + FILTER AND _ _ DECIMATOR f s LATCHED COMPARATOR (1-BIT ADC) B +V REF 1-BIT, K f s 1-BIT DATA STREAM 1-BIT DAC –V REF SIGMA-DELTA MODULATOR 8.20 a

  22. SIMPLIFIED FREQUENCY DOMAIN LINEARIZED MODEL OF A SIGMA-DELTA MODULATOR Q = 1 ( X – Y ) QUANTIZATION X – Y f NOISE Y X ANALOG FILTER ∑ ∑ H(f) = 1 + f _ Y 1 ( X – Y ) Y = + Q f REARRANGING, SOLVING FOR Y: X Q f + Y = f + 1 f + 1 SIGNAL TERM NOISE TERM 8.21 a

  23. SIGMA-DELTA MODULATORS SHAPE QUANTIZATION NOISE 2ND ORDER DIGITAL FILTER 1ST ORDER Kf s f s 2 2 8.22 a

  24. SECOND-ORDER SIGMA-DELTA ADC CLOCK INTEGRATOR INTEGRATOR Kf s V IN ∫ ∫ + + ∑ ∑ + _ _ _ 1-BIT DATA STREAM 1-BIT DAC DIGITAL FILTER AND DECIMATOR N-BITS f s 8.23 a

  25. SNR VERSUS OVERSAMPLING RATIO FOR FIRST, SECOND, AND THIRD-ORDER LOOPS 120 THIRD-ORDER LOOP* 21dB / OCTAVE 100 SECOND-ORDER LOOP 80 15dB / OCTAVE SNR (dB) 60 FIRST-ORDER LOOP 9dB / OCTAVE 40 * > 2nd ORDER LOOPS DO NOT 20 OBEY LINEAR MODEL 0 4 8 16 32 64 128 256 OVERSAMPLING RATIO, K 8.24 a

  26. EFFECT OF INPUT-REFERRED NOISE ON ADC "GROUNDED INPUT" HISTOGRAM NUMBER OF P-P INPUT NOISE OCCURANCES ≈ 6.6 × RMS NOISE RMS NOISE n–4 n–3 n–2 n–1 n n+1 n+2 n+3 n+4 OUTPUT CODE 8.25 a

  27. DEFINITION OF "NOISE-FREE" CODE RESOLUTION FULLSCALE RANGE EFFECTIVE = log 2 BITS RMS NOISE RESOLUTION NOISE-FREE FULLSCALE RANGE CODE RESOLUTION = log 2 BITS P-P NOISE P-P NOISE = 6.6 × RMS NOISE NOISE-FREE FULLSCALE RANGE log 2 BITS CODE RESOLUTION = 6.6 × RMS NOISE = EFFECTIVE RESOLUTION – 2.72 BITS 8.26 a

  28. AD7730 SINGLE-SUPPLY BRIDGE ADC AVDD DVDD REFIN(–) REFIN(+) AD7730 REFERENCE DETECT 100nA AIN1(+) STANDBY SIGMA-DELTA ADC AIN1(–) BUFFER + SIGMA- PROGRAMMABLE ∑ ∑ + SYNC MUX PGA DELTA DIGITAL _ MODULATOR FILTER +/– AIN2(+)/D1 MCLK IN AIN2(–)/D0 CLOCK 100nA SERIAL INTERFACE GENERATION 6-BIT MCLK OUT AND CONTROL LOGIC DAC REGISTER BANK SCLK VBIAS CS CALIBRATION MICROCONTROLLER DIN DOUT ACX AC EXCITATION ACX CLOCK POL AGND DGND RDY RESET 8.27 a

  29. AD7730 KEY SPECIFICATIONS I Resolution of 80,000 Counts Peak-to-Peak (16.5-Bits) for ± 10mV Fullscale Range I Chop Mode for Low Offset and Drift I Offset Drift: 5nV/°C (Chop Mode Enabled) I Gain Drift: 2ppm/°C I Line Frequency Common Mode Rejection: > 150dB I Two-Channel Programmable Gain Front End I On-Chip DAC for Offset/TARE Removal I FASTStep Mode I AC Excitation Output Drive I Internal and System Calibration Options I Single +5V Supply I Power Dissipation: 65mW, (125mW for 10mV FS Range) I 24-Lead SOIC and 24-Lead TSSOP Packages 8.28 a

Recommend

More recommend