A Performance-Constrained Template- A Performance-Constrained Template- Based Layout Retargeting Algorithm Based Layout Retargeting Algorithm for Analog Integrated Circuits for Analog Integrated Circuits Zheng Liu Lihong Zhang Liu Lihong Zhang Zheng Memorial University of Newfoundland Memorial University of Newfoundland St. John’ ’s, Canada s, Canada St. John
Overview Overview � Introduction Introduction � � Analog Layout Retargeting Design Flow Analog Layout Retargeting Design Flow � � Problem Formulation and Modeling Problem Formulation and Modeling � � MINLP MINLP- -Based Retargeting Algorithm Based Retargeting Algorithm � � Experimental Results Experimental Results � � Conclusions Conclusions �
Introduction Introduction � System System- -on on- -chip ( chip (SoC SoC) application necessitates ) application necessitates � analog design automation analog design automation � Layout Layout parasitics parasitics can be significantly sensitive to can be significantly sensitive to � analog circuit performances analog circuit performances � Rough estimation during the optimization phase Rough estimation during the optimization phase � � Analog circuits have become a design bottleneck Analog circuits have become a design bottleneck � for the growing mixed- -signal signal SoC SoC market market for the growing mixed � Special analog automated design tools are needed Special analog automated design tools are needed � for analog integrated circuits for analog integrated circuits
Review of Prior Work Review of Prior Work � Analog layout optimization tools have been Analog layout optimization tools have been � developed with limited design aspects developed with limited design aspects � A fully integrated constraint A fully integrated constraint- -driven analog driven analog � layout system (PARCAR) layout system (PARCAR) � Macro Macro- -cell based layout automation systems cell based layout automation systems � (including KOAN/ANAGRAM- -II, LAYLA, II, LAYLA, (including KOAN/ANAGRAM and ALADIN) and ALADIN) � IPRAIL IPRAIL – – Intel lecture Property Reuse Based Intel lecture Property Reuse Based � Layout Automation Layout Automation
Overview Overview � Introduction Introduction � � Analog Layout Retargeting Design Flow Analog Layout Retargeting Design Flow � � Problem Formulation and Modeling Problem Formulation and Modeling � � MINLP MINLP- -Based Retargeting Algorithm Based Retargeting Algorithm � � Experimental Results Experimental Results � � Conclusions Conclusions �
Analog Layout Retargeting Design Flow Analog Layout Retargeting Design Flow
Overview Overview � Introduction Introduction � � Analog Layout Retargeting Design Flow Analog Layout Retargeting Design Flow � � Problem Formulation and Modeling Problem Formulation and Modeling � � MINLP MINLP- -Based Retargeting Algorithm Based Retargeting Algorithm � � Experimental Results Experimental Results � � Conclusions Conclusions �
Problem Formulation & Modeling Problem Formulation & Modeling � Interconnect Parasitic Model Interconnect Parasitic Model � Parasitic resistance and capacitance for a Parasitic resistance and capacitance for a tile on a layer can be mathematically tile on a layer can be mathematically represented with its length length and and width : represented with its width : ρ sh × ( length / width ) R = ρ sh × ( length / width ) R = × (length × width)+c × (2 × length) a × (length × sw × (2 × C sub =c a width)+c sw length) C sub =c × ( length / distance ) C coup = c c c × ( length / distance ) C coup = c
Interconnect Modeling Interconnect Modeling � Resistance Resistance- -capacitance (RC) capacitance (RC) π -model is model is π - � used to represent resistance and capacitance used to represent resistance and capacitance of a net of a net ρ sh × ( R = ρ sh × (x x r - x x l )/ (y r - y y l ) R = r - l )/ (y r - l ) × (x × (y × 2 × (x a × ) × sw × 2 × C sub =c c a (x r - x x l (y r - y y l )+c sw (x r - x x l ) C sub = r - l ) r - l )+c r - l ) × ( c × C coup = c c (x x r - x x l ) / distance C coup = c r - l ) / distance
Performance and Matching Constraints Performance and Matching Constraints � To ensure the desired circuit performance, the To ensure the desired circuit performance, the � performance deviation must be restricted within a performance deviation must be restricted within a maximum allowed tolerance maximum allowed tolerance � Matching parasitic constraints are indispensable Matching parasitic constraints are indispensable � for the parasitic- -aware optimization problem aware optimization problem for the parasitic
Sensitivity Computation Sensitivity Computation � Performance sensitivity is utilized to quantify the Performance sensitivity is utilized to quantify the � dependence of circuit performance with respect to dependence of circuit performance with respect to parasitics parasitics / = ∂ ∂ S W p ij i j � The segmental sensitivity of The segmental sensitivity of W with respect to p is i with respect to j is W i p j � modeled using finite- -difference approximation difference approximation as as modeled using finite [ ( ) ( )] /( ) = − − S W p W p p p 1 2 1 2 ij ij ij
Central-Difference Sensitivity Central-Difference Sensitivity � Finite-difference approximation is not able to generally represent the expected sensitivity when p 1 is far away from p 2 � To manage desired performance, we advance the calculation to central-difference by assuming p 1 =p j_worst + Δ and p 2 = p j_worst - Δ [ ( ) ( )] / 2 = + Δ − − Δ Δ S W p W p _ _ ij ij j worst ij j worst � Sensitivity computation is conducted across parasitic upper bounds
Segmental Sensitivity Segmental Sensitivity � For less sensitive For less sensitive parasitics parasitics, the central , the central- -difference difference � approach can be used to generate plain upper- -bound bound approach can be used to generate plain upper sensitivities to approximately model the general sensitivities to approximately model the general impact of parasitics parasitics on performance on performance impact of � For sensitive nets, the sensitivities themselves are For sensitive nets, the sensitivities themselves are � very large and may vary significantly along with very large and may vary significantly along with changing parasitic values changing parasitic values � A piecewise sensitivity model is proposed to A piecewise sensitivity model is proposed to � accurately represent performance sensitivities for accurately represent performance sensitivities for sensitive parasitics parasitics sensitive
Piecewise Sensitivity Model Piecewise Sensitivity Model � Sensitivity analysis is conducted to identify the sensitive Sensitivity analysis is conducted to identify the sensitive � parasitics by running multiple simulations by running multiple simulations parasitics � Optimization flexibility ranges of these Optimization flexibility ranges of these parasitics parasitics are then are then � divided into a number of small segments divided into a number of small segments � Within each segment, the central Within each segment, the central- -difference sensitivity difference sensitivity � method is used to calculate its upper- -bound sensitivity bound sensitivity method is used to calculate its upper � Piecewise sensitivity can be built up as a linear function Piecewise sensitivity can be built up as a linear function � of binary- -integer variables and segmental sensitivities integer variables and segmental sensitivities of binary
Overview Overview � Introduction Introduction � � Analog Layout Retargeting Design Flow Analog Layout Retargeting Design Flow � � Problem Formulation and Modeling Problem Formulation and Modeling � � MINLP MINLP- -Based Retargeting Algorithm Based Retargeting Algorithm � � Experimental Results Experimental Results � � Conclusions Conclusions �
MINLP-Based Retargeting Algorithm MINLP-Based Retargeting Algorithm � The parasitic The parasitic- -aware analog layout retargeting aware analog layout retargeting � and optimization can be formulated as a two- - and optimization can be formulated as a two dimensional compaction problem dimensional compaction problem � By computing segmental sensitivities, the By computing segmental sensitivities, the � binary- -integer piecewise sensitivities construct integer piecewise sensitivities construct binary a set of coefficients a set of coefficients � Linear approximation is used for quick Linear approximation is used for quick � performance- -deviation evaluation deviation evaluation performance
Mixed Integer Non-linear Programming Mixed Integer Non-linear Programming - where where x x rr , x x ll , y y rr , and y y ll represent the boundaries - rr , ll , rr , and ll represent the boundaries N - N and refer to piecewise sensitivities of all the - and refer to piecewise sensitivities of all the ∑ cap res ∑ B n S B n S n n 1 1 n = = n required performances required performances
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