A new MDT-based L1 trigger for ATLAS Sebastian Nowak - PowerPoint PPT Presentation

A new MDT-based L1 trigger for ATLAS Sebastian Nowak nowak@mpp.mpg.de Max-Planck-Institut für Physik, Munich Young Scientist Workshop, Ringberg Castle July 23, 2013

The ATLAS Muon Spectrometer designed for LHC nominal luminosity: L = 10 34 cm − 2 s − 1 Precision tracking chambers Trigger chambers 1150 Monitored Drift Tube Chambers (MDT) 606 Resistive Plate Chambers (RPC) 32 Cathode Strip Chambers (CSC) 3588 Thin Gap Chambers (TGC) 2 / 21

The ATLAS MDT chambers Gas mixture: Ar / CO 2 (93 / 7) � 3 bar absolute pressure r Max. drift time: ≈ 700 ns Al tube wall W−Re wire 3 or 4 Single tube resolution: 80 µm drift tube layers Wire positioning accuracy: 0.05 mm ≈ 20 µm 30 mm Chamber tracking resolution: width: 1 −2 m ≈ 40 µm length: 1−6 m HV Support Frame RO 3 / 21

Muon tracks for different momenta RPC strip width ~30mm Example: Muon barrel RPC 3 RPC 2 RPC 1 schematic, not to scale p T = 20 GeV p T = 40 GeV p T = 10 GeV The sagitta in the barrel is ~ 24 mm for p T = 20 GeV RPC: Resistive Plate Chamber → Trigger chamber 4 / 21

LHC Long Term Schedule 5 / 21

Rates in the ATLAS Muon Spectrometer Neutrons, γ s and charged hadrons from secondary reactions in detector components and shielding cause high background rates Background rate increases proportional with the luminosity ⇒ Rate capability in the Big Wheels exceeded Expected cavern background occupancy y (L = 7 * 10 34 cm -2 s -1 ) EOL 12 m EML 10% 6 3% 5% 7% 5 10 BOL 1 2 3 4 5 6 5 4 EEL 2 8 3% 4% 8% 4 BML 1 2 3 4 5 6 1 3 3 6 EIL4 1 2 3 4 5 6 BIL 2 3% 5% 6% 10% 3 2 4 2 EIL End-cap 1 1 magnet 1 2 10% CSC 0 z 0 2 4 6 8 10 12 14 16 18 20 6 / 21

MDT read-out chain (now) Reference point for the search path RPC 3 The trigger logic Sector identifies high-p T Outer Logic candidates CSM Search path for MDT hits RPC 2 Middle CSM RPC 1 Inner CSM example barrel Trigger tower (schematic) MDT CSM: Chamber Service Modul readout RPC: Resistive Plate Chamber Use of more precise MDT information for triggering. 7 / 21

MDT read-out chain (proposed) Reference point for the search path The existing L1 trigger path is RPC 3 preserved The trigger logic Sector identifies high-p T Outer Logic candidates CSM Search path for MDT hits RPC 2 Middle CSM RPC 1 Additional fast read-out Inner CSM example barrel The existing Trigger tower (schematic) CSM: Chamber Service Modul readout structure RPC: Resistive Plate Chamber will be preserved Use of more precise MDT information for triggering. 8 / 21

ATLAS Muon Trigger and DAQ System Reference point for the search path RPC 3 The trigger logic identifies high-p T Sector Outer Logic candidates CSM Level 1: Trigger chamber Search path for MDT hits → MDT read-out RPC 2 Middle CSM RPC 1 Level 2: First track reconstruction Inner CSM example barrel Trigger tower (schematic) MDT CSM: Chamber Service Modul readout RPC: Resistive Plate Chamber New concept (Upgrade Phase 2): Level 0: Trigger chambers → MDT fast read-out Level 1: MDT chambers fast read-out → MDT read-out Level 2: First track reconstruction 9 / 21

ATLAS Muon Trigger and DAQ System Reference point for the search path The existing L1 trigger path is RPC 3 The trigger logic preserved identifies high-p T Sector Outer Logic candidates CSM Level 1: Trigger chamber Search path for MDT hits → MDT read-out RPC 2 Middle CSM RPC 1 Level 2: First track reconstruction Additional fast read-out Inner CSM example barrel Trigger tower (schematic) The existing CSM: Chamber Service Modul readout structure RPC: Resistive Plate Chamber will be preserved New concept (Upgrade Phase 2): Level 0: Trigger chambers → MDT fast read-out Level 1: MDT chambers fast read-out → MDT read-out Level 2: Track reconstruction 10 / 21

Performance of the existing L1 p T trigger The interesting physics is Total muon production cross section mainly at p T above ∼ 20 GeV (see W,Z cross section) p T = 20 GeV The slope of the inclusive p T Fake spectrum is rising very steeply triggers with decreasing p T − → threshold definition of the L1 trigger must be sharp to avoid high trigger rates from low p T muons ATLAS Level-1 muon trigger efficiency cross section for cross section for p T > 10 GeV: ∼ 400 nb p T > 20 GeV: ∼ 47 nb 11 / 21

Histogram based track finding algorithm for an additional MDT fast read-out preceding correct following bunch crossing bunch crossing bunch crossing t = − 1 t = 0 t = + 1 Bunch crossing: Time of muon production 12 / 21

Simulation framework Stand-alone Monte Carlo simulation Adjustable parameters: Drift tube chamber geometry Angle of incidence of the muon and spread of the angle Rate of non-correlated background Effect of δ -rays Inefficient regions (tube walls, glue gaps) are included Real r-t relation (implemented as look-up table) Performance studied as a function of the background rate with and without spread of the incident muon angle 13 / 21

Parameters used for all simulation Drift time resolution 25 ns ( ∼ 0.5 mm) Algorithm bin width 2 mm Angle of incidence (EML1) 0.123 < α < 0.238 [rad] Worst case scenario: EML1 Expected cavern background occupancy y (L = 7 * 10 34 cm -2 s -1 ) EOL 12 m EML 10% 6 3% 5 5% 7% 10 BOL 1 2 3 4 5 6 5 4 EEL 2 8 3% 8% 4% 4 BML 1 2 3 4 5 6 1 3 3 6 EIL4 1 2 3 4 5 6 BIL 2 3% 5% 6% 3 10% 2 4 2 EIL End-cap 1 1 magnet Chamber for 1 2 10% simulation CSC α 0 z 14 / 21 0 2 4 6 8 10 12 14 16 18 20

Definitions for simulation results Efficiency: Calculated track is within 2 mm region (bin width) of real track Fake probability without ROI (Region Of Interest): Calculated track is outside 2 mm region of real track The track fitting is not based on trigger chambers information Fake probability with ROI: Calculated track is within 3 cm ROI and outside 2 mm region of real track The track fitting is based on trigger chambers information 15 / 21

MDT Level-1 muon trigger simulation for EML1 No incidence angle spread With δ -rays 1 1 Efficiency Fake probability Minimum number of hits: 3 Minimum number of hits: 4 0.9 0.9 Trigger (within 2mm region of real track) Fake probability (within 3cm ROI) 0.8 0.8 Fake probability 0.7 0.7 Trigger efficiency 0.6 (hits > 4) 0.6 Trigger efficiency 0.5 0.5 (hits > 3) 0.4 0.4 0.3 0.3 0.2 0.2 0.1 0.1 0 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Background occupancy 10% Occupancy (3 hits required): Efficiency: 98.5% Fake probability with ROI: 0.2% Fake probability without ROI: 0.5% 16 / 21

Incidence angle spread Angle: α = 0.123 rad 1 Efficiency Minimum number of hits: 4 0.9 Efficiency: Within 2 mm region of real track 0.8 No δ -rays 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 Angle spread [mrad] Expected incidence angle spread for EML ( p T = 32 GeV): Trigger chamber information not available 20 mrad algorithm inefficient Trigger chamber information available 3 mrad minor degradation 17 / 21

Test of new read-out hardware (planned) CERN Gamma Irradiation Facility (GIF) Goal: Measurement of efficiency and resolution of additional fast read-out µ Scintillator Layer Lead Source Filters Lead Lead 137 Cs Scintillator Layer 150 GBq No muon beam in the GIF → use (low energy) cosmic muons Fast read-out and normal read-out are triggered by scintillators ⇒ Trigger chambers information is calculated out of muon tracks 18 / 21

Summary and Outlook HL-LHC luminosities lead to ATLAS muon spectrometer trigger rate problem → Proposal of an MDT-based additional trigger Simulation results for most difficult region (occupancy 10%): Efficiency: 98.5% Fake probability: 0.5% Hardware test setup in development First test planned in autumn 2013 19 / 21

New trigger implementation based on MDT Angular resolution of trigger chambers: 3.0 mrad Necessary angular resolution: 1.0 mrad Fast MDT read-out resolution: 25 ns / 12.5 ns → 0.5 / 0.26 [mm] → 1.7 / 0.9 [mrad] y EOL EML 12 m 6 RPCs 5 10 BOL 1 2 3 4 5 6 5 4 EEL 2 8 4 BML 1 2 3 4 5 6 1 3 3 6 EIL4 1 2 3 4 5 6 BIL 2 3 2 4 2 EIL TGCs End-cap 1 1 magnet 1 2 CSC 0 z 0 2 4 6 8 10 12 14 16 18 20 20 / 21

Hardware implementation MDT L0-Trigger Prototype Scheme MDT_FPGA_R2 Actel FPGA MDT chamber ASD HPTDC Serial configuration of ASDs Scintillator module Hit[23:0] ASD L0 Trigger Decoding L0 Counters ASD Unit / Board L0 Counter Serial Encoding Serial Interface Chip / Circuit Ready To be done 40-pin flat cable Test Setup Board Windows-PC Actel FPGA 3 phys. trigger inputs Software ENC (L1, ECR, EBR, GR) Test Setup Adaption Serial TDC data decoding Extension Analysis MC USB Data transfer to MC USB L0 Trigger Encoding L0 Serial Decoding 21 / 21