A Low Power Design of Gray and T0 Codecs for the Address Bus Encoding for System Level Power Optimization Prabhat K. Saraswat, Ghazal Haghani and Appiah Kubi Bernard Advanced Learning and Research Institute, ALaRI, University of Lugano, Switzerland ABSTRACT This report describes our attempt to design the Gray and T0 codecs to be used to encode the bits to be sent on the processor-memory address bus. Since switching is one of the most important contributors to the power consumption of VLSI circuits, it is imperative to encode the bits in such a way that the switching activity on the buses are reduced. However, it should also be understood that encoding does not always reduces power. The trade offs between power uti- lization of the codec hardware and the power reduction due to lessening of switching transitions has also been understood. Different codecs may perform differently for different address sequences. We have generated the sequences of addresses of specified sequentiality and evaluated the performance of both codecs. The codecs are designed and synthesized using VHDL/Synopsis Tools. The VHDL models are then simulated in order to measure the dynamic power consumed by them when the bits are encoded and decoded. The total power including the power consumed by the bus is calculated. Various comparisons are made with the uncoded binary scheme. An optimum bus capacitance is also calculated which makes the usage of codecs beneficial. We have also tried to implement another scheme where the bus lines are interchanged in order to reduce the power consumption due to crosstalk. The results obtained are discussed and explained in the report. Keywords: Gray Encoding, Zero Transition Encoding, Bus load 1. BUS ENCODING FUNDAMENTALS - GRAY AND T0 CODECS Bandwidth of data transfers have increased considerably due to the high speed needed between microprocessors and system interfaces. Considerable amount of power is needed at the I/O pins of a microprocessor due to intrinsic capacitance of the bus lines. By minimizing the switching transitions on the system level bus lines, dramatic optimization of average power consumption can be achieved. There are various bus encoding schemes that achieve this purpose, eg. Gray code and T0 code. 1 1.1. Gray Encoding It has been observed that the addresses generated by a program are often sequential in nature. The simplest way to encode the generated addresses is binary, which results in a lot of transitions thus increasing the switching activity. One of the often cited solutions for this was proposed by Su, Tsui and Despain 2 to use gray encoding to minimize the number of transitions. Gray encoding allows for only a single transition for consecutive addresses. 1.2. T0 Encoding The sequentiality of the addresses is transferred to the subsystem by adding an additional redundant line to the bus in order to avoid transfer of consecutive addresses. The redundant line is set to zero when 2 of the addresses in the bus are consecutive, this prevents unnecessary switching, and the receiver then calculates the new address. As it is clearly visible, the T0 code guarantees zero transitions as its asymptotic performance for in-sequence addresses 1 2. PROBLEM STATEMENT AND MOTIVATION An 16 bit address bus is assumed. Two bus encoding schemes, gray and T0 have to be implemented using VHDL. The program accesses to memory has to be modeled by generating address streams of varying sequentiality. The codecs are evaluated on the basis of switching activity and power consumption. Synthesization and evaluation of codec power consumption is done by using synopsis power compiler. The minimum bus load has to be calculated which makes the bus encoding convenient. The main motivation for the project is to be able to appreciate and understand the effectiveness of various encoding schemes for the address streams of different sequentiality. Further author information: (Send correspondence to Prabhat Kumar Saraswat) Prabhat Kumar Saraswat: E-mail: prabhat.saraswat@alari.ch, Telephone: 0041 786295106 1
3. DESIGN AND IMPLEMENTATION OF VHDL MODELS The first and foremost step is to design the VHDL models effectively to reduce the overheads due to the hardware of codec itself. The gray code and T0 codec were implemented. The gray encoding algorithm is implemented by comparing each bit with the next bit in the generated bit stream. For example, if the generated bit stream is represented as B ,the gray code will be a concatenation of B[i] xor B[i+1] where i is 0...n-1. The advantage of using gray algorithm before sending the data to the bus is that¡ we have less switching transitions and consequently less power usage. As the algorithm for encoding and decoding data is the same we can use same hardware to encode and decode the data. The hardware configuration for gray encoder and decoder implemented in VHDL is shown in figure1. The zero transition codec algorithm is very efficient for purely sequential addressing mode , In this case we need to define one extra line in our connection paths to use it as a flag. When system wants to access to sequential addresses in memory we just freeze the first address and by setting the flag receiver is informed to calculate the addresses from the base address. The hardware configuration for T0 coded implemented in VHDL is shown below: Figure 1. Implemented Hardware for GRAY and T0 CODEC respectively The corresponding VHDL codes can be seen in the attached appendix with this report. 4. ADDRESS SEQUENCE GENERATION WITH A SPECIFIED SEQUENTIALITY We have attempted to generate numbers with a specified sequentiality value. The objective of this attempt is to model the pattern of memory accesses from a processor when a software is run on it. The software in itself might be containing some loops where the sequential memory locations are accessed. However, there might be cases (branches etc.) when the memory accesses are not sequential. The problem to be addressed is how to model those cases when the accesses are not sequential. How to simulate those cases and generate the resulting address streams, when a specific value, say sequentiality percentage is defined. One primitive attempt to model this problem would be described here. However, this method is definitely not the best way to generate, but it is hoped that it would raise some questions and issues that would allow for further refinement and understanding of this problem. Our approach takes shape along with a basic argument that defines non sequentiality . Non sequentiality, as we can presume, is observed when a totally chaotic (random) distribution of numbers is generated. It refers to the stream generated when there is no correlation between the numbers. Thus we need a random number generator function to be able to generate such a stream. Let the minimum address accessed is 0, and the max address which can be reached is NUM .We have coded a function which generates a random number according to a uniform distribution: X is a Uniform Distirbution between (0 , NUM) We will now define two parameters a and b which would be defining the sequentiality levels in generated numbers. The number a and b are related as: b = 1 − a Both a and b have ranges between 0 and 1 and the value of a would define the sequentiality percentage. The final number generated could be calculated by a simple function. Let I(n) represent a sequential stream from 0 to 2
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