A 1.1V, 667MHz Random Cycle, , y , Asymmetric 2T Gain Cell Embedded DRAM with a 99 9 Percentile Retention DRAM with a 99.9 Percentile Retention Time of 110µsec Ki Chul Chun Pulkit Jain Ki Chul Chun, Pulkit Jain, Tae-Ho Kim, and Chris H. Kim University of Minnesota, Minneapolis, MN Symposia on VLSI Technology and Circuits
Outline • Motivation • Proposed Techniques for Enhancing oposed ec ques o a c g EDRAM Performance – Asymmetric 2T Gain Cell Asymmetric 2T Gain Cell – Current S/A with Pseudo-PMOS Diode – Half Swing Write Bit-line Driver Half Swing Write Bit line Driver – Stepped Write Word-line Technique • 65nm EDRAM Chip Measurements • Summary Slide 1
Embedded Memory Options [1] J Barth et al [1] J. Barth et al., ISSCC 07, [2] D. Somasekhar et al., ISSCC 08 ISSCC ’07 [2] D Somasekhar et al ISSCC ‘08 [3] K. Chun et al., VLSI Symp. ‘09 Slide 2
Random Cycle Comparison LP 65nm, 1.1V, 85 C LP 65nm 1 1V 85ºC 1.83ns 3T eDRAM +351ps +581ps WL enabling RBL ∆ 100 RBL ∆ 100mV (6 σ ) V (6 Latency: 1.94ns Sensing Refresh period: WBL driving 0.9ns 100 µs for 3T eDRAM Cell restoring (6 σ ) Cell restoring (6 σ ) 6T SRAM 6T SRAM Pre-charging Latency: 1.65ns 0 0 0.5 0.5 1 1 1.5 1.5 2 2 2.5 2.5 3 3 • Approaches to enhance eDRAM performance – 6T micro sense amplifier for 1T1C eDRAMs (IBM) – Boosted 3T gain cell (Univ. of Minnesota) – Asymmetric 2T gain cell (this work) Slide 3
Cell Retention Time Issue 65nm, 1.1V, 85ºC 65nm 1 1V 85ºC 1.2 Data 1 low limit 1.0 t( ∆ BL 200mV)= 500ps 0.8 0 8 w/ 256cells/BL 0.6 BIAS Read reference bias 0 4 0.4 t( ∆ REF 100mV)= 500ps w/ 256cells/BL 0.2 µs 0 0 5E-5 1E-4 1.5E-4 2E-4 2.5E-4 *1M Monte-Carlo simulations (3-NMOS gain cell) • Small storage capacitance of a gain cell – Rapid decrease of cell signal with large variations – Speed-determining data ‘1’ retention constraint S d d t i i d t ‘1’ t ti t i t Slide 4
Rationale of Asymmetric Gain Cell M. Ichihashi et al., VLSI Symp. ‘05 • PMOS write device compensates NMOS I GATE • I GATE prevailing bias � poor compensation • Goal: Keep the speed-determining data ‘1’ voltage close to VDD � Asymmetric 2T Gain Cell Slide 5
Proposed Asymmetric 2T Gain Cell 65nm, 1.1V, 85ºC , , 1.2 1 2 Asymmetric 3T 1.0 V BIAS_3T 0.8 ∆ =0.21V ge (V) 0.6 0 4 0.4 ode voltag 0.2 47.4 µs (BL delay=500ps) 0 1.2 Asymmetric 2T 1.0 Cell no ∆ 0 25V ∆ =0.25V V BIAS_2T 0.8 0.6 ∆ =0.25V 174.3 µs 0.4 (BL delay=300ps) 0.2 0 0 5E-5 1E-4 1.5E-4 2E-4 2.5E-4 Time after write (sec) • Data ‘1’ favorable (pull-up) leakages and low V TH Data 1 favorable (pull up) leakages and low V TH storage (read) device – 3.7X retention time improvement with 40% read bit- p line delay enhancement Slide 6
Read Bit-line Leakage in 2T eDRAM I I READ I I BIAS I LEAK I I I LEAK I LEAK I I LEAK I RBL RBLB RBLB V BIAS 1 1 1 1 1 0 0 S/A d Unselected D) Selected d D) d Unselected D) d Unselected D) d Unselected D) Selected d D) d Unselected D) (VDD (GND (VDD (VDD (VDD (GND (VDD Unselected (VDD) No RBL leakage Worst RBL leakage 65nm, 1.1V, 100ºC, Fast 65nm, 1.1V, 100ºC, Fast 1.2 1.2 RBL D0 RBL D0 tage (V) 1.0 tage (V) 1.0 ∆ =100mV ∆ =100mV 0.8 0.8 RBL D1 RBL REF 0.6 0.6 RBL REF Data 1 read Data 1 read REF 0.4 0 4 0.4 0 4 Volt RBL RBL D1 Volt failure! 0.2 0.2 RWL enable 0 0 0 0.5 1 1.5 2 2.5 3 0 0.5 1 1.5 2 2.5 3 Delay (nsec) Delay (nsec) • Very small voltage window results in read failure in worst case scenario – VDD pre-charged Current Sense-Amplifier (C-S/A) Slide 7
Previous Current S/As J Sim et al J. Sim et al., VLSI Symp. 02 VLSI Symp ‘02 E Seevinck et al E. Seevinck et al., VLSI Symp. ‘90 VLSI Symp ‘90 • Limited voltage headroom (left) and impedance matching issue (right) t hi i ( i ht) Slide 8
Proposed Pseudo-PMOS Diode C-S/A Current RBLL RBLR P1 Read bias I IN I INB 1 1 1 1 SA SAB P2 lected (GND) lected (VDD) lected (GND) lected (VDD) VBB Pseudo Pse do Se Unse Se Unse PMOS diode Leakages SAEN (gm P2 gm P1 ) VDD > V TH + V OV + 2V DS,SAT Rin = where, |VBB| |V TH | where, |VBB| > |V TH | (gm P1 )(gm P2 ) (gm P1 )(gm P2 ) • Simple and stable impedance matching with enhanced voltage headroom h d lt h d Slide 9
Read Bit-line Delay Comparison ) rcentile (%) Pe • Read bit-line delay of the proposed 2T eDRAM is Read bit line delay of the proposed 2T eDRAM is similar to that of an SRAM – 1Mb macro distributions with cell voltage distributions, g , includes random V TH variations and C-S/A mismatches Slide 10
Half Swing Write Bit-line Driver Sense amplifier & Write-back circuit & read port write port RBLR RBLL WBLR SA SA SA SAB SAB VBB WBLL WBLL • Performance advantages over conventional GND pre-charged WBL scheme pre charged WBL scheme – ~50% faster switching time and 25% smaller WBL charging current consumption on average – 2.4% retention time improvement Slide 11
Stepped Write Word-line Technique VPP (VDD+0.3V) WWLB WWL ADDR RSET PUPVDDB PDNGND • Boosted high (VPP) and low (VBB) supplies are Boosted high (VPP) and low (VBB) supplies are standard in DRAMs to prevent signal loss • Two step WWL to reduce charge pump overhead Two step WWL to reduce charge pump overhead – 67% power saving of boosted supplies and 4.4% chip size reduction compared to level shifters – Narrow WWL pulse width (-25%) issue Slide 12
Write Performance Comparison rent (A) (%) Percentile ( Cur V) Voltage (V P V • Write device of a gain cell is a simple pass gate Write device of a gain cell is a simple pass gate – Excellent data ‘1’ write margin crucial for read – Sufficient WWL window for data ‘0’ (required = 179ps, ( q p , achieved = 406ps @ 667MHz random cycle) Slide 13
192kb Test Macro Architecture • 192 cells per WL, 512 cells per split BL architecture which share common BL-S/A and write driver Slide 14
EDRAM Test Chip Microphotograph LUMN DECODER SA & WBACK BLS COL CTRL • 667MHz random cycle at a 110 μ sec retention time and a 99.9% bit yield condition • Retention time increases to 1200 μ sec for 500MHz Slide 15
Automated Retention Time Measurement • Measurement bench: LabView TM controlled pattern generator and logic analyzer (left) • Measured retention time bitmap of a 1kb sub- array at 1.5ns random cycle time (right) Slide 16
Impact of VPP Level on Retention Time 100 100 1.1V, 85ºC VPP=1.4~1.6V, 0.05V step 80 Data 1 with 60 increasing VPP increasing VPP 40 20 0 Data 0 1.E+02 1.E+03 1.E+04 Retention time ( µ sec) • Strong VPP dependency of retention time can be exploited for exploited for – Finding optimal retention time considering both data ‘0’ and data ‘1’ cases – Post-fabrication trimming to cope with D2D variations Slide 17
Random Cycle Time Measurement 4 1.E+04 99.9% bit yield at 85ºC me ( n sec) ( µ sec) ( µ sec) 3 1.E+03 ntion time ( m cycle tim ntion time 2 1.E+02 Random Reten Reten 1 1.E+01 Retention time Cycle time 0 1.E+00 0.8 0 8 0 9 0.9 1 1 1 1 1.1 1.2 1 2 1.3 1 3 1.4 1 4 VDD (V) • 667MHz (500MHz) random cycle and 110µs (1200µs) retention time at 1.1V, 85 ° C, and 99.9% bit yield condition (left) • Wide operating voltage range of 0.8V ~ 1.4V (right) Wid ti lt f 0 8V 1 4V ( i ht) Slide 18
Summary (1/2) • Gain cell eDRAM as an alternative for high density memory – 2.4X higher bit cell density than SRAM – Generic logic process and decoupled read/write path enables the potential of better performance than 1T1C enables the potential of better performance than 1T1C eDRAM • Proposed circuit techniques to improve read p q p speed and enhance retention time – Asymmetric 2T Gain Cell – Current S/A with Pseudo-PMOS Diode – Half Swing Write Bit-line Driver – Stepped Write Word-line Technique St d W it W d li T h i Slide 19
Summary (2/2) • A 1.1V, 65nm 192kb eDRAM chip with 512 cells per BL architecture demonstrated – 667MHz random cycle at 1.1V, 85 ° C, and a 99.9% retention time of 110 μ sec – 248 μ W per Mbit static power dissipation at 1 2V 85 ° C 248 μ W per Mbit static power dissipation at 1.2V, 85 C, 500MHz random cycle and 1200 μ sec retention time – Measured latencies are 1.39ns/1.65ns at 1.2V/1.1V, 85 ° C Acknowledgements: Broadcom, a Scholarship from Samsung Electronics, and an IBM Faculty Partnership Award Partnership Award Slide 20
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