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55:035 Computer Architecture and Organization Lecture 11 Outline - PowerPoint PPT Presentation

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55:035 Computer Architecture and Organization Lecture 11 Outline Interrupts Program Flow Multiple Interrupts Nesting IO Architecture Bus Types Transfer Methods Disks Disk Arrays 55:035 Computer

  1. 55:035 Computer Architecture and Organization Lecture 11

  2. Outline  Interrupts  Program Flow  Multiple Interrupts  Nesting  IO  Architecture  Bus Types  Transfer Methods  Disks  Disk Arrays 55:035 Computer Architecture and Organization 2

  3. Interrupts  Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing  Program  e.g. overflow, division by zero  Timer  Generated by internal processor timer  Used in pre-emptive multi-tasking  I/O  from I/O controller  Hardware failure  e.g. memory parity error 55:035 Computer Architecture and Organization 3

  4. Interrupt Cycle  Added to instruction cycle  Processor checks for interrupt  Indicated by an interrupt signal  If no interrupt, fetch next instruction  If interrupt pending:  Suspend execution of current program  Save context  Set PC to start address of interrupt handler routine  Process interrupt  Restore context and continue interrupted program 4

  5. Transfer of Control via Interrupts 5

  6. Program Flow Control 6

  7. Program Timing Short I/O Wait 7

  8. Program Timing Long I/O Wait 8

  9. Multiple Interrupts  Disable interrupts  Processor will ignore further interrupts whilst processing one interrupt  Interrupts remain pending and are checked after first interrupt has been processed  Interrupts handled in sequence as they occur  Define priorities  Low priority interrupts can be interrupted by higher priority interrupts  When higher priority interrupt has been processed, processor returns to previous interrupt 9

  10. Multiple Interrupts - Sequential 55:035 Computer Architecture and Organization 10

  11. Multiple Interrupts – Nested 55:035 Computer Architecture and Organization 11

  12. Time Sequence of Multiple Interrupts 55:035 Computer Architecture and Organization 12

  13. Input/Output & System Performance Issues  System Architecture & I/O Connection Structure Types of Buses/Interconnects in the system.   I/O Data Transfer Methods.  Cache & I/O: The Stale Data Problem  I/O Performance Metrics.  Magnetic Disk Characteristics.  Designing an I/O System & System Performance: Determining system performance bottleneck.   (which component creates a system performance bottleneck) 55:035 Computer Architecture and Organization 13

  14. The Von-Neumann Computer Model  Partitioning of the computing engine into components: Central Processing Unit (CPU): Control Unit (instruction decode, sequencing of  operations), Datapath (registers, arithmetic and logic unit, buses). Memory: Instruction (program) and operand (data) storage.  Input/Output (I/O): Communication between the CPU and the outside world  Input Control Memory I/O - Subsystem (instructions, Datapath data) Output registers ALU, buses I/O Devices CPU Computer System System performance depends on many aspects of the system (“limited by weakest link in the chain”) 14

  15. Input and Output (I/O) Subsystem  The I/O subsystem provides the mechanism for communication between the CPU and the outside world (I/O devices).  Design factors:  I/O device characteristics (input, output, storage, etc.).  I/O Connection Structure (degree of separation from memory operations).  I/O interface (the utilization of dedicated I/O and bus controllers).  Types of buses (processor-memory vs. I/O buses).  I/O data transfer or synchronization method (programmed I/O, interrupt-driven, DMA). 55:035 Computer Architecture and Organization 15

  16. Typical System Architecture System Bus or Front Side Bus (FSB) Memory Controller (Chipset North Bridge) I/O Controller Hub (Chipset South Bridge) Isolated I/O I/O Subsystem 16

  17. System Components Time(workload) = Time(CPU) + L1 CPU Time(I/O) - Time(Overlap) (possibly L2 on-chip) Important issue: Which component L3 creates a system performance Caches (FSB) bottleneck? System Bus SDRAM PC100/PC133 100-133MHz Bus Adapter Main I/O Bus 64-128 bits wide Memory 2-way inteleaved Controller Example: PCI, 33-66MHz ~ 900 MBYTES/SEC )64bit) 32-64 bits wide 133-528 MB/s Memory Bus NICs PCI-X 133MHz 64-bits wide I/O Controllers Double Date 1066 MB/s Rate (DDR) SDRAM Memory PC3200 Disks 200 MHz DDR 64-128 bits wide Displays Networks 4-way interleaved Keyboards ~3.2 GBYTES/SEC (64bit) Chipset Chipset I/O Devices RAMbus DRAM (RDRAM) North South I/O Subsystem 400MHZ DDR Bridge Bridge 16 bits wide (32 banks) ~ 1.6 GBYTES/SEC 55:035 Computer Architecture and Organization 17

  18. I/O Interface I/O Interface, I/O controller or I/O bus adapter:  Specific to each type of I/O device.  To the CPU, and I/O device, it consists of a set of control and data registers (usually memory-mapped) within the I/O address space.  On the I/O device side, it forms a localized I/O bus which can be shared by several I/O devices  (e.g IDE, SCSI, USB ...)  Handles I/O details (originally done by CPU) such as:  Assembling bits into words,  Low-level error detection and correction Processing off-loaded  Accepting or providing words in word-sized I/O registers. from CPU  Presents a uniform interface to the CPU regardless of I/O device. 55:035 Computer Architecture and Organization 18

  19. I/O Controller Architecture Chipset Chipset Peripheral or Main I/O Bus (PCI, PCI-X, etc.) North Bridge South Bridge Peripheral Bus Interface/DMA Host Memory Micro-controller or Buffer Embedded processor Memory µProc Processor Cache ROM Host I/O Channel Interface Processor I/O Contr oller SCSI, IDE, USB, …. 19

  20. Types of Buses in The System (1/2)  Processor-Memory Bus  System Bus, Front Side Bus, (FSB)  Should offer very high-speed (bandwidth) and low latency.  Matched to the memory system performance to maximize memory-processor bandwidth.  Usually design-specific (not an industry standard).  Examples:  Alpha EV6 (AMD K7), Peak bandwidth = 400 MHz x 8 = 3.2 GB/s  Intel GTL+ (P3), Peak bandwidth = 133 MHz x 8 = 1 GB/s  Intel P4, Peak bandwidth = 800 Mhz x 8 = 6.4 GB/s  HyperTransport 2.0: 200Mhz-1.4GHz, Peak bandwidth up to 22.8 GB/s (point-to-point system interconnect not a bus) 20

  21. Types of Buses in The System (2/2)  I/O buses (sometimes called an interface):  Follow bus industry standards.  Usually formed by I/O interface adapters to handle many types of connected I/O devices.  Wide range in the data bandwidth and latency  Not usually interfaced directly to memory instead connected processor-memory bus via a bus adapter (chipset south bridge).  Examples:  Main system I/O bus: PCI, PCI-X, PCI Express  Storage: SATA, IDE, SCSI. 55:035 Computer Architecture and Organization 21

  22. Intel Pentium 4 System Architecture (Using The Intel 925 Chipset) CPU System Bus (Front Side Bus, FSB) (Including cache) Bandwidth usually should match or exceed that of main memory Memory Controller Hub (Chipset North Bridge) System Memory Two 8-byte DDR2 Channels Graphics I/O Bus (PCI Express) Storage I/O (Serial ATA) Main Misc. I/O Bus I/O (PCI) Interfaces Misc. I/O I/O Controller Hub Interfaces (Chipset South Bridge) I/O Subsystem 55:035 Computer Architecture and Organization 22

  23. Bus Characteristics Option High performance Low cost/performance Bus width Separate address Multiplex address & data lines & data lines Data width Wider is faster Narrower is cheaper (e.g., 64 bits) (e.g., 16 bits) Transfer size Multiple words has Single-word transfer less bus overhead is simpler Bus masters Multiple Single master (requires arbitration) (no arbitration) Split Yes, separate No , continuous transaction? Request and Reply connection is cheaper packets gets higher and has lower latency bandwidth (needs multiple masters) Clocking Synchronous Asynchronous 23

  24. Storage IO Interfaces/Buses IDE/Ultra ATA SCSI Data Width 16 bits 8 or 16 bits (wide) Clock Rate Upto 100MHz 10MHz (Fast) 20MHz (Ultra) 40MHz (Ultra2) 80MHz (Ultra3) 160MHz (Ultra4) Bus Masters 1 Multiple Max no. devices 2 7 (8-bit bus) 15 (16-bit bus) Peak Bandwidth 200 MB/s 320MB/s (Ultra4) 55:035 Computer Architecture and Organization 24

  25. I/O Data Transfer Methods (1/2)  Programmed I/O (PIO): Polling (For low-speed I/O)  The I/O device puts its status information in a status register.  The processor must periodically check the status register.  The processor is totally in control and does all the work.  Very wasteful of processor time.  Used for low-speed I/O devices (mice, keyboards etc.) Time(workload) = Time(CPU) + Time(I/O) - Time(Overlap) 55:035 Computer Architecture and Organization 25

  26. I/O Data Transfer Methods (2/2)  Interrupt-Driven I/O (For medium-speed I/O):  An interrupt line from the I/O device to the CPU is used to generate an I/O interrupt indicating that the I/O device needs CPU attention.  The interrupting device places its identity in an interrupt vector.  Once an I/O interrupt is detected the current instruction is completed and an I/O interrupt handling routine (by OS) is executed to service the device.  Used for moderate speed I/O (optical drives, storage, neworks ..)  Allows overlap of CPU processing time and I/O processing time 55:035 Computer Architecture and Organization 26

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