3D slim edge silicon sensors: Processing, Yield and QA Cinzia Da Viá , Uni. Manchester. HSTD-8 Taipei 5 th December 2011 for the ATLAS IBL production Cinzia Da Vià, The University of Manchester, UK GF Dalla Betta (Trento University), G. Pellegrini, C. Fleta (CNM Barcelona) M. Boscardin , G. Giacomini, N. Zorzi(FBK Trento)A. Kok, T-E Hansen (SINTEF), J. Hasi, C. Kenney (SLAC), S, Parker (Hawaii). S. Grinstein (IFAE), A. Micelli (Udine), C. Gemme, G. Darbo (Genova) D-L Pohl (Bonn). Introduction 3D silicon for the ATLAS IBL Quality Assurance Production Yield Summary and outlook CNM
Introduction The Large Hadron Collider will have its first upgrade in 2013-14 to • Cinzia Da Viá , Uni. Manchester. HSTD-8 Taipei 5 th December 2011 reach its nominal energy of 14TeV in the center of mass ATLAS will use the LHC Upgrade time to insert an extra pixel layer • 33mm from the beam. For this to be possible the current beam pipe will be replaced with a smaller diameter one (More on this from S. Grisnstein on Tuesday) Diamond, 3D and new planar silicon sensors with slim edges were • competing as sensor technologies for the IBL After one year of intense qualification work and looking at all risks • involved a review panel recommended to load the IBL with 75% planar and 25% 3D silicon sensors Diamond will be used to build a beam condition monitor in the IBL • region (see A. Gorisek) More on 3D sensors from G. Pellegrini and M. Povoli and some details • on the common IBL 2011 test beams results from I. Rubinskiy
ATLAS IBL Layout and parameters Layout – 14 Staves Cinzia Da Viá , Uni. Manchester. HSTD-8 Taipei 5 th December 2011 – 14 FE chips/stave – For 3D single chips (224 to build 25%) – For planar double chips (448 to build 75%) These numbers have a redundancy of 100% to account for loading yield Requirements – “Hermetic” to straight tracks in Φ (1.8º overlap) – No overlap in Z: minimize gap between sensor active area. Parameters – IBL envelope: 9 mm in R – <R> = 33 mm. – Z = 60 cm (active length). – η = 2.5 coverage.
IBL sensors specifications Cinzia Da Viá , Uni. Manchester. HSTD-8 Taipei 5 th December 2011 FE-I3 18 FE-I4 160 FE-I4A-B FE-I3 FE-I4 Pixel Size [ μ m 2 ] 50×400 50×250 250 m m Pixel Array 18×160 80×336 Chip Size [mm 2 ] 7.6×10.8 20.2×19.0 TDAC Active Fraction 74 % 89 % Amp2 50 m m Analog Current [ μ A/pix] 26 10 synthezised digital region (1/4 th ) Digital Current [ μ A/pix] 17 10 discri Analog Voltage [V] 1.6 1.4 Preamp Digital Voltage [V] 2 1.2 FDAC Config Logic pseudo-LVDS out [Mb/s] 40 160
3D detectors particle ~ 0.2-1mm PLANAR 3D Cinzia Da Viá , Uni. Manchester. HSTD-8 Taipei 5 th December 2011 particle guard rings p + 50 m m 50 m m 300 m m n + p + n + 300 m m Active edge diffusion - i - - - - - - - - - - + + + + + + + + n + MEDICI DICI simulatio mulation 3D 3D planar nar of a 3 3D struc ructure n DEPLETION VOLTAGES < 10 V 70 V After irradiation 180 V 1000V Power dissipation goes with V goes with V EDGE SENSITIVITY < 5 m m 500 m m CHARGE 1 MIP (300 mm) 24000e - 24000e - e CAPA CITANCE 30-50f ~20fF COLLECTION DISTANCE 50 m m 300 m m SPEED 1-2ns 10-20 ns 3D has Lower charge sharing probability Drif ift t lines s parall rallel l to the surf rface ce
3D sensors for IBL 3 Cinzia Da Viá , Uni. Manchester. HSTD-8 Taipei 5 th December 2011 3D is a silicon sensor technology designed specifically to be radiation hard The current design parameters have been tuned to optimize the IBL constraints in terms of signal amplitude, noise, bias voltage and consequent system requirements First prototypes were available at the end of 1990ties. Few years later more industries started producing 3D sensors In June 2009, four facilities decided to „join‟ knowhow and effort for a common goal: optimise the process and speedup a parallel industrialization strategy to guarantee a reliable production of 3D sensors. Two were finally selected for the „fast track‟ ATLAS IBL. The remaining two still contribute to the effort and looking into future optimizations of the design Common on floor-plan lan wafer r layou out
Original Strategy: qualify both full3D and DSDC with Common Floor-Plan Design Design by GF Dalla Betta, C. Kenney, A. Kok, G Pellegrini Cinzia Da Viá , Uni. Manchester. HSTD-8 Taipei 5 th December 2011 FE-I4 full 3D with Active Edges wafer 8 8 x FE-I4 I4 Fabricated at SINTEF • 9 9 x FE-I3 I3 J Hasi, C. Kenney, With holes filled • Other er test t A. Kok, T-E Hansen structures tures At Stanford -1.0 0 10 20 30 40 50 60 70 80 -3.0 Leakage Current (µA) -5.0 -7.0 -9.0 -11.0 -13.0 -15.0 Bias Voltage (V) FE-I4 1 FE-I4 2 FE-I4 3 FE-I4 4 FE-I4 5 FE-I4 6 FE-I4 7 FE-I4 8
QA and Sensor selection criteria Each wafer should have at least 3 good FE-I4 3D sensors to be selected. Cinzia Da Viá , Uni. Manchester. HSTD-8 Taipei 5 th December 2011 QA action Level Description/Comments Visual inspection Each fabrication step Check for shorts, discoloration or anomalies on the sensor surface, front – back misalignment Wafer bow completed Measurement of wafer bow, no problem wafer for bump-bonding but potential risk of higher leakage and electrodes misalignment Critical steps analysis with test wafers DRIE Optical inspection, test of resistance, Poly-doping presence of voids or anomalies IV on test structures Completed wafer Gives a global indication of wafer quality. Test structures are distributed all around the wafer perimeter where IV would indicate worst case. IV on FE-I4 sensors On wafer and Useful to select good sensors after Used by CNM after UBM process completion and after UBM deposition. Requires a guard ring Use of temporary metal On wafer Gives a reliable measurement of the Used by FBK sensor quality at pixel level, performed before final metal deposition. X-Ray inspection at IZM After UBM Performed at IZM 8 After bump-bonding
3D sensors Selection Parameters The following specifications are required to qualify a 3D device as functioning correctly before bump-bonding: Cinzia Da Viá , Uni. Manchester. HSTD-8 Taipei 5 th December 2011 • Operation at room temperature (20−24 o C) • Vdepl ≤ 15V • Vop ≥ Vdepl +10V where Vdepl is the full depletion voltage. • Current at 20 − 24 o C at operation voltage: I (Vop ) < 2μA per sensor • For GR measurement (CNM): IGR ( Vop) < 200nA per sensor • Breakdown voltage: Vbd > 25V • Slope: [I( Vop)/I(Vop-5V)] < 2 I-V measurements are performed on each sensor on wafer with a probe station by the manufacturer using either a temporary metal or by probing the guard ring current 9 FBK temporary metal CNM guard ring current
CNM IBL Qualification wafers before and after bump-bonding 25 C. Fleta. S. Grinstein, G. Pellegrini Cinzia Da Viá , Uni. Manchester. HSTD-8 Taipei 5 th December 2011 Wafer 12 Wafer 17 GR current on wafer vs total current after bonding, GR current on wafer vs total current after bonding, 100 100 20ºC 20ºC W17 W12 6/8 10 10 4/8 12-4-chip 17-4-chip 17-4-wafer 12-4-wafer 17-1-chip 12-1-chip I(uA) 1 1 I(uA) 17-1-wafer 12-1-wafer 17-2-chip 12-8-chip 17-2-wafer 12-8-wafer 0.1 17-3-chip 0.1 17-3-wafer 12-6-chip '17-7-chip 12-6-wafer '17-7-wafer 0.01 0.01 0 50 100 150 200 0 50 100 150 200 V(V) V(V) Wafer 15 GR current on wafer vs total current after bonding, GR current identifies potential 100 20ºC W16 defects 4/8 10 15-4-chip 15-4-wafer Also could be enhanced by stress and 15-1-chip I(uA) 1 neighbour sensors 15-1-wafer 15-5-chip 15-5-wafer 0.1 100% Reproduced behaviour before 15-2-chip 15-2-wafer and after BB 0.01 0 50 100 150 200 10 V(V)
Compilation qualification CNM assemblies after BB I< 2 m A Vop ≥ Vdepl +10V (20V) Cinzia Da Viá , Uni. Manchester. HSTD-8 Taipei 5 th December 2011 Vbd > 25V Slope: [I(Vop)/I(Vop-5V)] < 2
3D IBL production: technical sheet for each of the selected wafers: ex. CNM 7 Cinzia Da Viá , Uni. Manchester. HSTD-8 Taipei 5 th December 2011 bowing
Yield production run : CNM 1 G Pellegrini, C. Fleta Cinzia Da Viá , Uni. Manchester. HSTD-8 Taipei 5 th December 2011 4 5 8 6 3(+2) 6 WAFERS sent for bump-bonding Yield on selected wafers 42/64=66% 5 5 13
Cinzia Da Viá , Uni. Manchester. HSTD-8 Taipei 5 th December 2011 Selection Criteria and QA - FBK
FBK ATLAS09 Wafer 14 : selected for bump-bonding N. Zorzi, G. Giacomini FEI4 sensors - total current Cinzia Da Viá , Uni. Manchester. HSTD-8 Taipei 5 th December 2011 1E+06 1E+05 #5 1E+04 I [nA] 1E+03 S1 S2 S3 S4 1E+02 S5 S6 S7 S8 1E+01 0 10 20 30 40 50 60 70 80 V_rev [V] Temporary metal shorts together a • #6 full column of pixel. All columns IV measured separately • and summed up together. Metal etched off before being sent • for bump-bonding
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