2012 H4IRRAD test campaigns Summary of results S. Uznanski CERN, Geneva, Switzerland Radiation Working Group meeting Oct 16, 2012
2012 H4IRRAD test campaigns 3 H4IRRAD slots have been defined in 2012 1 st slot – May 15, 2012 – June 3, 2012 MAX5541 – 16-bit DAC ADS1281 – Delta-Sigma ADC DS18B20 – 1-wire thermometer DS2401 – 1-wire ID SPLargeUHD9 – 130nm SP SRAM 2 nd slot – Aug 03, 2012 – Aug 17, 2012 MAX5541 – 16-bit DAC MIC37302 – Voltage regulator 3 rd slot – Nov 15, 2012 – Dac 3, 2012 MIC37302 – Voltage regulator FGClite proto S. Uznanski, RadWG 2 Oct 16, 2012
2012 H4IRRAD test campaigns 3 H4IRRAD slots have been defined in 2012 1 st slot – May 15, 2012 – June 3, 2012 DS18B20 – 1-wire thermometer DS2401 – 1-wire ID MAX5541 – 16-bit DAC ADS1281 – Delta-Sigma ADC SPLargeUHD9 – 130nm SP SRAM 2 nd slot – Aug 03, 2012 – Aug 17, 2012 MAX5541 – 16-bit DAC MIC37302 – Voltage regulator 3 rd slot – Nov 15, 2012 – Dac 3, 2012 MIC37302 – Voltage regulator FGClite proto S. Uznanski, RadWG 3 Oct 16, 2012
DS18B20/DS2401 (1/3) DUT description: DUT name DUT type Test type Samples Package Date code Lot code tested DS18B20 1-wire SEE, TID 2 x 25 TO-92 unknown unknown thermometer DS2401 1-wire ID SEE, TID 2 x 25 SOT-223 9931C2 DM914705AIB Tester architecture and test procedure: CONTROL ROOM H4IRRAD INTERNAL ZONE X 25 PC FTDI Driver DS2401 DS2401 DS2401 DS2401 DS2401 USB . . . TX/RX ~40m FT232M DS2408 ABPC11505 . . . DS18B20 DS18B20 DS18B20 DS18B20 DS18B20 USB FTDI Driver DS2401 DS2401 DS2401 DS2401 DS2401 . . . TX/RX ~40m FT232M DS2408 . . . DS18B20 DS18B20 DS18B20 DS18B20 DS18B20 Read Detect Err Read Detect Err Read Th Detect Err S/N IDs in S/N IDs Th IDs in Th IDs temp in Th temp S. Uznanski, RadWG 4 Oct 16, 2012
DS18B20/DS2401 (2/3) Beam conditions: Dose in 1 Si MeV thermal Run start Run end HEH per cm2 Gy ± Neq ± neutrons ± Run ± 50% date date 50% 50% x2 1 May 15, 2012 @ May 22, 2012 @ 4.5E+01 8.1E+10 3.3E+11 3.8E+10 3:05pm 12:30pm 2 May 22, 2012 @ May 25, 2012 1.8E+01 3.3E+10 1.3E+11 1.5E+10 02:07pm @02:11pm 3 May 25, 2012 @ Jun 04, 2012 8.1E+01 1.5E+11 5.9E+11 6.9E+10 02:11pm @09:41am SEE test results: S/N Th Run start Run end S/N ID Th ID Th temp Run Iterations comm Comm date date err err err err Err May 15, 2012 @ May 22, 2012 @ 1 19217 0 0 0 9 6 3:05pm 12:30pm May 22, 2012 @ May 25, 2012 2 7621 0 0 0 2 1 02:07pm @02:11pm May 25, 2012 Jun 04, 2012 3 27229 0 0 0 87 6 @02:11pm @09:41am S. Uznanski, RadWG 5 Oct 16, 2012
DS18B20/DS2401 (3/3) 28 200 Temperature drift: 180 Measured temperature (deg C) 27 160 140 26 Dose in Si (Gy) 120 25 100 80 Temp Th1 (deg C) 24 60 Temp Th2 (deg C) 40 23 20 Dose in Gy 22 0 0 500000 1000000 1500000 2000000 time (s) Conclusions: Temperature measurement drift observed during the slot is equal to 3.3e-2 ± 1.2 ° C/Gy Dose (Gy) S/N ID err S/N comm err Th ID err Th Comm Err Th temp err Component ± 50% (cm2/HEH) (cm2/HEH) (cm2/HEH) (cm2/HEH) (cm2/HEH) S/N (DS2401) 143 <4.4E-12 <4.4E-12 X x x Th (18B20) 143 x x <4.4E-12 5.6E-10 9.2E-11 S. Uznanski, RadWG 6 Oct 16, 2012
MAX5541 (1/2) DUT description: DUT DUT type Test Samples Packag Date code Lot code name Type tested e MAX5541 16-bit DAC TID, 3 DIP/SO unknown unknown SEE Tester architecture and test procedure: CONTROL ROOM H4IRRAD INTERNAL ZONE X 3 DUT DAC DUT FGC2 DAC DUT PC DIN, CLK, CS DIN, CLK, CS Multilink Card RS232 DAC DUT H4IRRAD tests Fan-out for DUTs ABPC11505 ~50m (boot program) +5V, +/-15V Ctrl Card DataLogger RS232 Analog Out Agilent 34970A Power meas ~50m 15 DUT1 DAC out DUT2 DAC out 10 DUT3 DAC out DAC output (V) 5 Data Logger Run FGC DAC Ramp generation 0 Initialization test program for DAC -5 -10 -15 200 250 300 350 400 450 500 time (min) S. Uznanski, RadWG 7 Oct 16, 2012
MAX5541 (2/2) Beam conditions: DUT Dose in Gy ± Test start Test end HEH per cm2 1 Si MeV thermal neutrons num ± 50% Neq ± 50% ± x2 date date 50% 1 15/05/2012 04/06/2012 1.35E+02 2.14E+11 8.61E+11 1.18E+11 12:01 16:56 2 15/05/2012 04/06/2012 1.23E+02 2.02E+11 8.54E+11 1.16E+11 12:01 16:56 3 15/05/2012 04/06/2012 1.18E+02 1.90E+11 8.18E+11 1.12E+11 12:01 16:56 Results: Components have been irradiated up to 135, 123 and 118 Gy, no power consumption increase after irradiation, all components fully functional No SEL have been detected No SEFI/SETs have been observed during the slot SEL XS upper level < 3.80e-12 SEU/SEFI XS upper level < 3.80e-12 S. Uznanski, RadWG 8 Oct 16, 2012
ADS1281 (1/2) DUT description: DUT DUT type Test Samples Packag Date code Lot code name Type tested e ADS1281 High-Res TID, 3 TSSOP- unknown unknown ADC SEE 24 Tester architecture and test procedure: CONTROL ROOM H4IRRAD INTERNAL ZONE X 3 DUT FGC2 PC RS232 H4IRRAD tests FGC DAC DAC DUT ABPC11505 DAC DUT (boot program) +5V, +/-15V FGC DAC ADC DUT ~50m DataLogger Ctrl Card RS232 Analog Out Agilent 34970A Power meas ~50m VME PAL Mdulator Out ~50m Processing unit Copper to optics 2 ADC Input voltage (V) 1 DUT4 ADC Driver 0 DUT5 ADC Driver DUT6 ADC Driver Data Logger Run FGC ADC Ramp generation -1 Initialization test program for ADC -2 13500 13600 13700 13800 13900 14000 Time (min) S. Uznanski, RadWG 9 Oct 16, 2012
ADS1281 (2/2) Beam conditions: DUT HEH per Dose in Gy ± num Test start Test end 1 Si MeV thermal cm2 Neq ± 50% neutrons ± x2 date date 50% ± 50% 1 15/05/2012 04/06/2012 1.28E+02 2.50E+11 1.00E+12 1.24E+11 12:01 16:56 2 15/05/2012 04/06/2012 1.64E+02 2.34E+11 9.49E+11 1.19E+11 12:01 16:56 3 15/05/2012 04/06/2012 1.32E+02 2.21E+11 9.05E+11 1.23E+11 12:01 16:56 Results: Components have been irradiated up to 164, 132 and 128 Gy No SEL have been detected: SEL XS upper level < 8.06E-13 No SEFI/SETs have been observed during the slot SEFI XS upper level < 8.06E-13 SEU on M0 upper level < 1.31E-12 SEU on M1 upper level < 1.53E-12 No significant power consumption increase have been observed S. Uznanski, RadWG 10 Oct 16, 2012
SPLargeUHD9 (1/2) DUT description: DUT name DUT type Test Samples Package SRAM generator Lot code Type tested version SPLargeUHD CMOS TID, SEE 1 x 4Mbit PBGA 6.1.1@20021219.0 unknown chip 1 SRAM 256+16 SPLargeUHD CMOS TID, SEE 1 x 4Mbit PBGA 6.1.1@20021219.0 unknown chip 2 SRAM 256+16 Tester architecture and test procedure: ON TOP OF THE SHIELDING CONTROL ROOM H4IRRAD INTERNAL ZONE PSU 2 x 50pins comm ~10m SRAM1 ~35m Ethernet Tester 2 x 50pins comm PC SRAM2 Altera dvp kit power 1 x 9pins DUT card PSU FI 1363 PC Tester Altera dvp kit Initializ Write Read Detect ation pattern pattern errors S. Uznanski, RadWG 11 Oct 16, 2012
SPLargeUHD9 (2/2) Beam conditions: Dose in 1 Si MeV thermal Test start Test end HEH per cm2 Gy ± Neq ± neutrons ± ± 50% date date 50% 50% x2 ‘A’/‘5’ 15/05/2012 22/05/2012, 5.2E+01 9.2E+10 3.0E+11 4.0E+10 15:00 14:54:45 23/05/2012, 25/05/2012, ‘A’/‘5’ 2.1E+01 3.7E+10 1.2E+11 1.6E+10 10:42:30 14:07:52 25/05/2012, 04/06/2012, ‘0’/‘1’ 9.4E+01 1.7E+11 5.4E+11 7.2E+10 15:52:16 09:02:25 15/05/2012 04/06/2012, ‘0’/‘1’ 1.6E+02 3.0E+11 9.6E+11 1.3E+11 15:00 09:02:25 SEE test results: #MBU Events Events SEU XS MBU XS Total XS Run #SEU (2) Chip1 Chip2 (cm2/bit) (cm2/bit) (cm2/bit) 1 53084 193 24716 28368 6.9E-14 7.7E-17 6.9E-14 (0xAA/0x55) 2 18645 1462 8579 10066 6.0E-14 1.5E-15 6.3E-14 (0x00/0xFF) 3 86000 7118 39547 46453 6.1E-14 1.6E-15 6.5E-14 (0x00/0xFF) S. Uznanski, RadWG 12 Oct 16, 2012
2012 H4IRRAD test campaigns 3 H4IRRAD slots have been defined in 2012 1 st slot – May 15, 2012 – June 3, 2012 DS18B20 – 1-wire thermometer DS2401 – 1-wire ID MAX5541 – 16-bit DAC ADS1281 – Delta-Sigma ADC SPLargeUHD9 – 130nm SP SRAM 2 nd slot – Aug 03, 2012 – Aug 17, 2012 Not performed MAX5541 – 16-bit DAC MIC37302 – Voltage regulator 3 rd slot – Nov 15, 2012 – Dac 3, 2012 MIC37302 – Voltage regulator FGClite proto S. Uznanski, RadWG 13 Oct 16, 2012
2012 H4IRRAD test campaigns 3 H4IRRAD slots have been defined in 2012 1 st slot – May 15, 2012 – June 3, 2012 DS18B20 – 1-wire thermometer DS2401 – 1-wire ID MAX5541 – 16-bit DAC ADS1281 – Delta-Sigma ADC SPLargeUHD9 – 130nm SP SRAM 2 nd slot – Aug 03, 2012 – Aug 17, 2012 MAX5541 – 16-bit DAC MIC37302 – Voltage regulator 3 rd slot – Nov 15, 2012 – Dac 3, 2012 MIC37302 – Voltage regulator FGClite proto S. Uznanski, RadWG 14 Oct 16, 2012
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