Xylem: Enhancing Vertical Thermal Conduction in 3D Processor-Memory - PowerPoint PPT Presentation

Xylem: Enhancing Vertical Thermal Conduction in 3D Processor-Memory Stacks Aditya Agrawal, Josep Torrellas and Sachin Idgunji University of Illinois at Urbana Champaign and Nvidia Corporation http://iacoma.cs.uiuc.edu MICRO, October 2017

Xylem 2 Image source: http://repasosdeharold.blogspot.com/2015/02/plants-test-review.html

Motivation: Thermal Issues in 3D Stacking Processor-Memory Stacks: ▪ Reduced interconnect length and power ▪ Higher memory bandwidth ▪ Smaller form factors ▪ Heterogeneous integration ▪ 2.5D processor-memory stacks exist ▪ 3D processor-memory stacking is the future Major challenge: Thermals 3 Xylem, MICRO 2017

3D Stacking Technologies TTSV Silicon TSV Upper Die Devices (Face) M1 2 μ m Frontside Metal Layers Mn Electrical Dummy 20 μ m μ bump μ bump D2D Layer 2 μ m BM1 Backside Metal Layers Lower Die (Back) TTSV TSV Silicon Face-to-back (f2b) die interface (not to scale) 4 Xylem, MICRO 2017

Stack Organization: Memory on Top ✓ Processor power and I/O signals Heat Sink do not traverse TSVs Integrated Heat Spreader (IHS) ✓ Processor IR drop similar to current Thermal Interface Material (TIM) DRAM Silicon designs Die to Die (D2D) Layer ✓ DRAM and processor die floorplans DRAM Frontside Metal (Al) are independent because TSV count and location are governed by Through Silicon Vias (TSVs) stacked DRAM standards Processor Silicon Processor Frontside Metal (Cu)  Thermal challenges C4 pads Package 5 Xylem, MICRO 2017

Contributions ▪ Identify the thermal bottleneck in 3D stacks: Die-to-Die(D2D) layers ▪ Improve vertical conduction through the D2D layer: – Align and short dummy μbumps with Thermal TSVs – Generic and custom TTSV placement schemes ▪ Use the resulting thermal headroom: – Boost processor frequency (400-720 MHz) & performance (11-18%) ▪ Exploit thermal heterogeneity: cores closer to TTSVs conduct heat better – Conductivity-aware thread placement and migration, and frequency boosting 6 Xylem, MICRO 2017

Thermal Resistance in the Stack ▪ Thermal resistance per unit area: R th (mm 2 -K/W) Layer Bulk Silicon 0.83 Proc. Metal 1.00 D2D 13.33 D2D layer is 13-16x more resistive than bulk silicon or metal layers 7 Xylem, MICRO 2017

Shortcomings of Prior Work ▪ Underestimated the thermal resistance of D2D layer by assuming: – High conductivity – Small thickness ▪ Focused on increasing the conductivity of the bulk silicon using TTSVs ▪ Concluded that TTSVs alone are effective Our approach: Combine TTSVs with a mechanism to reduce D2D resistance 8 Xylem, MICRO 2017

Propose: Dummy μ bump-TTSV Alignment & Shorting Before Proposed Upper Die (Face) Upper Die (Face) Frontside Frontside Metal Metal TTSV Silicon TTSV Silicon Layers Layers Dummy Dummy D2D D2D Underfill Underfill μ bump μ bump Lower Die (Back) Lower Die (Back) Backside Backside TTSV Metal Metal TTSV Silicon Silicon Layers Layers 9 Xylem, MICRO 2017

TTSV Placement: Constraints TTSVs: ▪ Cannot disrupt regular DRAM arrays: Place in the DRAM peripheral logic ▪ Distribute TTSVs and avoid TTSV farms ▪ Maintain Keep Out Zone (KOZ) around each TTSV Dummy μ bumps: Anywhere in the D2D layer except the electrical μ bump locations ▪ 10 Xylem, MICRO 2017

DRAM and Processor Baseline Floorplans Core 1 Core 2 Core 3 Core 4 DL1 DL1 DL1 DL1 IL1 IL1 IL1 IL1 Memory L2 L2 L2 L2 Controllers TSV Bus Coherent Bus TSV Bus Logic L2 L2 L2 L2 Core 5 Core 6 Core 7 Core 8 Bank DL1 DL1 DL1 DL1 IL1 IL1 IL1 IL1 DRAM (Wide IO) die floorplan Processor die floorplan 11 Xylem, MICRO 2017

Proposal: TTSV Placement Schemes TTSV TSV Bus TSV Bus TTSV Bank Bank Generic (oblivious to hotspots) Custom (aligned with hotspots) 12 Xylem, MICRO 2017

Proposal: Frequency Boosting ▪ TTSV placement & TTSV- μbump alignment and shorting: – Increases thermal conduction from the processor die to the heat sink – Reduces the temperature of the processor die ▪ Proposal: Increase processor frequency to consume the thermal headroom – Increase application performance 13 Xylem, MICRO 2017

Proposal: Conductivity ( λ ) Aware Techniques ▪ TTSV- μbump alignment and shorting creates high conductivity paths – Areas closer to TTSVs dissipate heat more easily – Result is thermal spatial heterogeneity in the stack ▪ Proposal: Three λ -aware optimizations to further improve performance – λ -aware thread placement – λ -aware frequency boosting – λ -aware thread migration 14 Xylem, MICRO 2017

Evaluation Setup Heat Sink ▪ 8-core OoO processor die @ 2.4 GHz IHS ▪ TIM 8 high Wide IO memory on top DRAM Silicon D2D Layer ▪ Processor timing and power: SESC & McPAT DRAM Metal ▪ DRAM timing and power: DRAMSim2 ▪ Thermal analysis: 3D HotSpot TSVs ▪ Applications: SPLASH-2, PARSEC & NAS Proc. Silicon Proc.Metal C4 pads Motherboard Memory-on-top configuration 15 Xylem, MICRO 2017

Result Summary TTSV Placement Generic Custom Area Overhead 0.63% 0.81% 5.0 o C 8.4 o C Proc. Temp. Reduction Avg. Frequency Boost 400 MHz 720 MHz Avg. Performance Gain 11% 18% λ -aware techniques enable further 100-200 MHz improvements 16 Xylem, MICRO 2017

Conclusion ▪ Identified that D2D layer is the thermal bottleneck in 3D stacks ▪ Improved vertical conduction through the D2D layer: – Align and short dummy μbumps with TTSVs – Generic and custom TTSV placement schemes ▪ Used the resulting thermal headroom to – Boost processor frequency (400-720 MHz) & performance (11-18%) ▪ Exploited thermal heterogeneity: cores closer to TTSVs conduct heat better – Conductivity-aware thread placement and migration, and frequency boosting – Enable further 100-200 MHz improvements 17 Xylem, MICRO 2017

Xylem: Enhancing Vertical Thermal Conduction in 3D Processor-Memory Stacks Aditya Agrawal, Josep Torrellas and Sachin Idgunji University of Illinois at Urbana Champaign and Nvidia Corporation http://iacoma.cs.uiuc.edu 18