Welcome to the Atomic Scale Era: New Paradigms and Processes for Continued Scaling May 12, 2017 Robert D. Clark Senior Member of the Technical Staff TEL Technology Center, America, LLC
TEL TECHNOLOGY CENTER, AMERICA, LLC. LEADING-EDGE R&D CAPABILITY The SUNY Polytechnic Institute Colleges of Nanoscale Science and New Zero Energy Nanotechnology Engineering’s Albany NanoTech Campus (ZEN) Building E C B D A 2003 04 05 06 07 08 09 10 11 12 13 14 15 A WORLD-CLASS TEAM LITHOGRAPHY ACCESS TTCA* First III-V Data DCS Enabled LFLFLE First MOSCAP Data 90+ engineers ASML 1700i 1.2NA/50nm l/s Founded First DSA Data Solid Source Fin Doping 60+ service/support ASML 1950i 1.35NA/35nm l/s 7nm SiN/SiO 2 ALE NanoFab North First Full Flow ASML NXE3300B 0.33NA/18nm l/s C 40 TEL tools in a Transistor Data New Fab NFX E 4000+ sq ft cleanroom 50,000 sq ft cleanroom INTEGRATED PROCESSING – TEL TOOLS 300/450mm compatible NanoFab Central D NanoFab South Annex Coater/Developer Tools 12 A 3 TEL tools installed 18 TEL tools in a 13 TEL tools in a FEOL/BEOL Tools 42 4000+ sq ft cleanroom 4000+ sq ft cleanroom Metrology/Test Tools 26 First Full Flow 1.6nm LER w/DCS and NTD B NanoFab South FinFET Data First 7nm MIS contacts 6 TEL tools in a 2000+ sq ft cleanroom First Si ALE Robert D. Clark/ TTCA-TFPT / 05122017.01 2 TEL is a registered trademark or a trademark of Tokyo Electron Limited in Japan and /or other countries
Outline Background Technology and Scaling Trends Patterning Challenges and Approach Process technology examples New Directions for High K Materials New Contact Structures Summary Robert D. Clark/ TTCA-TFPT / 05122017.01 3
Background Robert D. Clark/ TTCA-TFPT / 05122017.01 4
Welcome to the Atomic Scale Era- There’s No Longer Plenty of Room at the Bottom. Scaling is Taking Longer… Projected 10nm 10nm Actual* CGP 54 54 MX 43 36 Fin 33 34 *Mistry Intel TMD March 28, 2017 But So Far it is Still Delivering. Historical and Projected Atomic Feature Sizes (half pitch/0.235 nm/Si atom) in CMOS High Volume Manufacturing. Projected feature sizes are based on Intel historical trend through 14nm manufacturing. Robert D. Clark/ TTCA-TFPT / 05122017.01 5
So What Happens When We Run out of Room at the Bottom? Source: dailymail.co.uk We Do What We’ve Always Done: We Go Up Robert D. Clark/ TTCA-TFPT / 05122017.01 6
Technology and Scaling Trends Robert D. Clark/ TTCA-TFPT / 05122017.01 7
Technology Trend: Going Vertical Nano-wire 3D Architecture FinFET Planar 3D NAND large stack High AR of DRAM [nm] 1000 ArF immersion i-Line 180 KrF 100 130 110 90 65 45 32 EUV 22 14 10 Scaling Resolution 10 Wavelength 7 5 1 1990 1993 1996 1999 2002 2005 2008 2011 2014 2017 2020 Vertical utilization is the key approach towards sub-10nm generation Robert D. Clark/ TTCA-TFPT / 05122017.01 8
Scaling Trend – Sub-lithographic Patterning Metal Pitch 193i 100 SE Poly Gate Pitch N22 80 n masks SADP Min. Metal Pitch (nm) 60 N14 EUV CD SE challenge 40 SAQP N10 SADP N7 1 mask 1 mask 20 N5 (SAMP) Alignment challenge Design layout change from 2D to 1D 0 0 20 40 60 80 100 Contacted Gate Pitch (nm) Complex and fine patterning technology is required for further scaling Robert D. Clark/ TTCA-TFPT / 05122017.01 9
Technology Trend: Self-(Something) Revolution Self-Aligned Self-Limited Self-Aligned Double Patterning Atomic Layer Deposition Self-Aligned Contact Mircea and Hsu MPT Short Course SPIE 2015 Auth VLSI 2014 Säynätjoki 8 May 2012, SPIE Newsroom. Self-Directed DOI: 10.1117/2.1201204.004218 Atomic Layer Etching Younkin SPIE 2015 Kim JES EDL 158, 12, 2011, D710-4 doi: 10.1149/2.061112jes Robert D. Clark/ TTCA-TFPT / 05122017.01 10
Patterning Challenges and Approach Robert D. Clark/ TTCA-TFPT / 05122017.01 11
Self-Aligned Multi-Patterning (Example 193i based SAQP) 3. 1 st Spacer 7. 2 nd Mandrel 6. 2 nd Spacer 4. 1 st Mandrel 5. 2 nd Core 2. 1 st Core Etch Depo Pull 1. Grid Litho depo Pull Etch Adapted from Mohanty and Smith SPIE 2017 ( 𝜏 𝐷𝐸−1 ( 1 2) 2 = 𝟏. 𝟔 𝒐𝒏 ) 2 = 𝜏 𝐹𝑄𝐹 = 2 Robert D. Clark/ TTCA-TFPT / 05122017.01 12
Patterning challenges to EPE SAQP Line cutting with LELELE Final Pattern 𝐹𝑄𝐹 = 𝑔(CD variation, Pattern OL) Mandrel, spacer, cuts • Previous Pattern • (EPE : Edge Placement Error) Traditional sources of CD variation • Cuts to the grid • Roughness • Cuts to each other • EPE control is critical for further extension Robert D. Clark/ TTCA-TFPT / 05122017.01 13
Patterning paradigm towards placement accuracy Self-Alignment + Self-Assembly Top-Down Self-Alignment Selective Deposition Lithography + DSA ALD / ALE Multiple Bottom-Up Multi color Patterning + Lithography Shorter LEx Shrink Wavelength SAMP Immersion EUV i-line KrF ArF The paradigm is expanding to self-alignment and bottom up approach Robert D. Clark/ TTCA-TFPT / 05122017.01 14
Patterning Challenges and Approaches Typical Challenge Potential Approach Scheme Grid SADP LER, LWR, local CDU Etch smoothing (DCS) • formation SAQP • Spacer reshape Spacer leaning Dep / cure and trim • Cost PR mandrel • Cut / Block LEx CD, CDU, CER Healing, shrink • Alignment with grid (within layer) SAB • Cost and complexity mitigation • EUV Self- Via/Contact LEx CD, CDU, CER Healing, shrink • Something formation Alignment with metal lines (inter layers) FSAV, SAC, SAGC • Cost and complexity mitigation EUV • New process Atomic level process ALE / ALD • development Bottom up lithography • Selective deposition Robert D. Clark/ TTCA-TFPT / 05122017.01 15
Process Technology Examples Robert D. Clark/ TTCA-TFPT / 05122017.01 16
Self-alignment through etch selectivity Intended Design Conventional approach Self-aligned approach (using L/S grid) (using three grid colors) C B A B C B A B C B A B C SAB (Self-aligned Block) Etch selects mandrel Etch selects fill material A = Mandrel B = Spacer C = Fill material self-alignment of cut/block is enabled by SAB, using etch selectivity Robert D. Clark/ TTCA-TFPT / 05122017.01 17
EPE margin improvement by SAB Conventional SAB (pitch assumption : 24nm) 12 12 36 36 half pitch half pitch etch etch Lithography OL is restricted to be Lithography OL limit will be covered within 6nm (regardless of 193i or EUV) within the margin EPE margin of hard mask is 3 times relaxed Robert D. Clark/ TTCA-TFPT / 05122017.01 18
EPE Improvement through Self-Aligned Gate Contact (SAGC) MD GC MD GC ILD Gate Gate ILD Gate Gate cap cap cap cap Gate Spacer Gate Spacer GC Open Gate Spacer Gate Spacer Gate Spacer Gate Spacer Gate Spacer Gate Spacer Gate Gate Gate Gate Multi-color approach Gate Stack with 2 enabling Self-alignment hole masks Self-alignment to gate cap, gate spacer and ILD Robert D. Clark/ TTCA-TFPT / 05122017.01 Adapted from Mohanty and Smith SPIE 2017 19
Bottom-up lithography Selective Deposition DSA < Metal on Metal > Hole Pitch Multiplication L/S Pitch Multiplication growth growth M M M D M D M D M D D D D D M M M M x4 multiplication x3 multiplication capable at 30nm pitch capable at 30nm pitch < Dielectric on Dielectric > growth self-assembly D D D D D M D M D M D D : Dielectric M : Metal LKR : Low-k Restoration DSA : Directed Self-Assembly Clark AVS 2015 Bottom-up lithography enables self-alignment and self-assembly Robert D. Clark/ TTCA-TFPT / 05122017.01 20
Selective deposition: Metal on Metal CD: 46.4nm growth 6.2nm Ru 106.9nm SiO2 W Ru W 50nm X-TEM EDX mapping 200nm 41.7nm growth SiO2 Ru 37.7nm Ru W Deposition of Ru is demonstrated to grow on W only Robert D. Clark/ TTCA-TFPT / 05122017.01 21
New Directions for High K – Teaching a New Dog Old Tricks Robert D. Clark/ TTCA-TFPT / 05122017.01 22
Selective deposition: Dielectric on Dielectric (Al 2 O 3 on TOX, not on Si) Si Substrate Treatment: HDHD - HDHD: cyclical deposition and low-temperature plasma hydrogen (SPA H) treatment - Sustained H-termination on Si - Delayed ALD Al 2 O 3 incubation 10:1 Thickness 4-5nm selectivity SPA H plasma effective in suppressing Al 2 O 3 growth up to ~5nm on Si and not on oxides Robert D. Clark/ TTCA-TFPT / 05122017.01 23
Anisotropic atomic layer etching of high K films 1 cycle 50 Al 2 O 3 BCl 3 40 ER=4Å/cycle Ar Amount etched (Å) 30 Plasma 20 Min Microelectronic Eng. 110 ( 2013 ) 457 – 460 10 0 0 2 4 6 8 10 12 14 ALE cycle (#) Robert D. Clark/ TTCA-TFPT / 05122017.01 24
Area Selective Deposition by Combining ALD and Etching ALD High K Dielectrics followed by Anisotropic Etching enables Ultra- Thin ALD Sidewall Spacers HfO 2 Note: Very good selectivity to SiO 2 Al 2 O 3 Robert D. Clark/ TTCA-TFPT / 05122017.01 25
Ferroelectric HfZrO 5nm TiN/7nm Hf 0.2 Zr 0.8 O 2 /Si + 700 o C 30 sec. PMA Adapted From: Sonal Day et. al. FCNM 2017 Also See: Sharma et. al. VLSI 2017 accepted - coming to Kyoto in June Robert D. Clark/ TTCA-TFPT / 05122017.01 26
New Contact Structures Robert D. Clark/ TTCA-TFPT / 05122017.01 27
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