Veriolog Overview Hardware Description Languages HDL CS/EE 3710 Designed to be an alternative to schematics Fall 2010 for describing hardware systems Two main survivors VHDL Commissioned by DOD Based on ADA syntax Verilog Designed by a company for their own use Based on C syntax Verilog Origins Verilog Developed as a proprietary HDL by You can think of it as a programming Gateway Design Automation in 1984 langauge Acquired by Cadence in 1989 BUT, that can get you into trouble! Made an open standard in 1990 Better to think of is as a way to describe Made an IEEE standard in 1995 hardware IEEE standard Revised in 2001 Begin the design process on paper Plan the hardware you want Use Verilog to describe that hardware Quick Review Quick Review (2001 syntax) Module name (args…); Module name (parameters, inputs, outputs); begin begin parameter ...; // define parameters wire … ; // internal wires input …; // define inputs reg …; // internal regs output …; // define outputs // the parts of the module body are wire … ; // internal wires // executed concurrently reg …; // internal regs, possibly output // the parts of the module body are <continuous assignments> // executed concurrently <always blocks> <continuous assignments> endmodule <always blocks> endmodule 1
Quick Review Verilog Description Styles Continuous assignments to wire vars Verilog supports a variety of description assign variable = exp; styles Results in combinational logic Structural Procedural assignment to reg vars explicit structure of the circuit e.g., each logic gate instantiated and connected Always inside procedural blocks (always to others blocks in particular for synthesis) Hierarchical instantiations of other modules blocking Behavioral variable = exp; program describes input/output behavior of circuit many structural implementations could have non-blocking same behavior variable <= exp; e.g., different implementation of one Boolean Can result in combinational or sequential function logic Synthesis: Data Types Synthesis: Data Types Possible Values (wire and reg): Register declarations 0: logic 0, false reg a; \\ a scalar register 1: logic 1, true reg [3:0] b; \\ a 4-bit vector register Z: High impedance output g; \\ an output can be a reg Digital Hardware reg g; The domain of Verilog output reg g; \\ Verilog 2001 syntax Either logic (gates) Wire declarations Or storage (registers & latches) Verilog has two relevant data types wire d; \\ a scalar wire wire wire [3:0] e; \\ a 4-bit vector wire reg output f; \\ an output can be a wire Number Syntax Parameters Numbers with no qualifiers are Used to define constants considered decimal parameter size = 16, foo = 8; 1 23 456 etc. wire [size-1:0] bus; \\ defines a 15:0 bus Can also qualify with number of digits and number base base can be b, B, h, H, d, D, o, O 4'b1011 // 4-bit binary of value 1011 234 // 3-digit decimal of value 234 2'h5a // 2-digit (8-bit) hexadecimal of value 5A 3'o671 // 3-digit (9-bit) octal of value 671 4b'1x0z // 4-bit binary. 2nd MSB is unknown. LSB is Hi-Z. 3.14 // Floating point 1.28e5 // Scientific notation 2
Synthesis: Assign Statement Synthesis: Basic Operators The assign statement creates Bit-Wise Logical combinational logic ~ (not), & (and), | (or), ^ (xor), ^~ or ~^ (xnor) assign LHS = expression ; Simple Arithmetic Operators LHS can only be wire type Binary: +, - expression can contain either wire or reg type Unary: - mixed with operators Negative numbers stored as 2’s complement wire a, c; reg b; output out; Relational Operators assign a = b & c; <, >, <=, >=, ==, != assign out = ~(a & b); \\ output as wire Logical Operators wire [15:0] sum, a, b; ! (not), && (and), || (or) wire cin, cout; assign a = (b > ‘b0110) && (c <= 4’d5); assign {cout,sum} = a + b + cin; assign a = (b > ‘b0110) && !(c > 4’d5); Synthesis: More Operators Synthesis: Operand Length Concatenation When operands are of unequal bit length, {a,b} {4{a==b}} { a,b,4’b1001,{4{a==b}} } the shorter operator is zero-filled in the most significant bit position Shift (logical shift) << left shift wire [3:0] sum, a, b; wire cin, cout, d, e, f, g; >> right shift assign a = b >> 2; // shift right 2, division by 4 assign sum = f & a; assign a = b << 1; // shift left 1, multiply by 2 assign sum = f | a; assign sum = {d, e, f, g} & a; Arithmetic assign sum = {4{f}} | b; assign a = b * c; // multiply b times c assign a = b * ‘d2; // multiply b times constant (=2) assign sum = {4{f == g}} & (a + b); assign a = b / ‘b10; // divide by 2 (constant only) assign sum[0] = g & a[2]; assign a = b % ‘h3; // b modulo 3 (constant only) assign sum[2:0] = {3{g}} & a[3:1]; Synthesis: Operand Length Synthesis: Extra Operators Operator length is set to the longest member Funky Conditional (both RHS & LHS are considered). Be careful. cond_exp ? true_expr : false_expr wire [3:0] a,b,c; wire d, sel; wire [3:0] sum, a, b; wire cin, cout, d, e, f, g; assign a = d ? b : c; // Mux with d as select wire[4:0]sum1; assign a = (b == c) ? (c + ‘d1): ‘o5; // good luck assign {cout,sum} = a + b + cin; Reduction Logical assign {cout,sum} = a + b + {4’b0,cin}; Named for impact on your recreational time Unary operators that perform bit-wise operations on a single operand, reduce it to one bit assign sum1 = a + b; &, ~&, |, ~|, ^, ~^, ^~ assign sum = (a + b) >> 1; // what is wrong? assign d = &a || ~^b ^ ^~c; 3
Synthesis: Assign Statement Synthesis: Assign Statement The assign statement is sufficient to The assign statement is sufficient to create all combinational logic create all combinational logic What about this: What about this: assign a = ~(b & c); assign a = ~(b & c); assign c = ~(d & a); assign c = ~(d & a); B A C D Simple Behavioral Module Simple Behavioral Module // Behavioral model of NAND gate // Behavioral model of NAND gate module NAND (out, in1, in2); // Verilog 2001 syntax output out; module NAND ( input in1, in2; output out; assign out = ~(in1 & in2); input in1, in2); endmodule assign out = ~(in1 & in2); endmodule Simple Behavioral Module Simple Structural Module // Behavioral model of NAND gate // Structural Module for NAND gate module NAND ( module NAND ( output out; output out; input in1, in2); input in1, in2); wire w1; // local wire // Uses Verilog builtin nand function // call existing modules by name // syntax is function id (args); // module-name ID ( signal-list ); nand i0(out, in1, in2); AND2X1 u1(w1, in1, in2); endmodule INVX1 u2(out,w1); endmodule 4
Simple Structural Module Procedural Assignment // Structural Module for NAND gate Assigns values to register types module NAND ( They involve data storage output out; The register holds the value until the next input in1, in2); procedural assignment to that variable wire w1; The occur only within procedural blocks // call existing modules by name initial and always // module-name ID ( signal-list ); initial is NOT supported for synthesis! // can connect ports by name... They are triggered when the flow of AND2X1 u1(.Q(w1), .A(in1), .B(in2)); execution reaches them INVX1 u2(.A(w1), .Q(out)); endmodule Always Blocks Synthesis: Always Statement The always statement creates… When is an always block executed? always @sensitivity LHS = expression ; always @sensitivity controls when Starts at time 0 LHS can only be reg type expression can contain either wire or reg type mixed with always @(a or b or c) operators … Logic Whenever there is a change on a, b, or c reg c, b; wire a; Used to describe combinational logic always @(a, b) c = ~(a & b); always @(posedge foo) always @(*) Whenever foo goes from low to high c = ~(a & b); Used to describe sequential logic … Storage always @(negedge bar) reg Q; wire clk; always @(posedge clk) Whenever bar goes from high to low Q <= D; Procedural Control Statements Multi-Way Decisions Conditional Statement Standard if-else-if syntax if ( <expression> ) <statement> if ( <expression> ) <statement> If ( <expression> ) else <statement> <statement> “else” is always associated with the closest else if ( <expression> ) previous if that lacks an else. <statement> You can use begin-end blocks to make it more clear else if ( <expression> ) if (index >0) <statement> if (rega > regb) else <statement> result = rega; else result = regb; 5
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