UT DA Hierarchical and Analytical Hierarchical and Analytical Pla - PowerPoint PPT Presentation

UT DA Hierarchical and Analytical Hierarchical and Analytical Pla Placement T cement Technique echniques for s for High High- Performa Performance A nce Analog C nalog Circuit ircuits Biying Xu, Shaolan Li, Xiaoqing Xu, Nan Sun, and David Z. Pan ECE Department, University of Texas at Austin ISPD, March 20 th , 2017 1

Outline Outline High-Performance Analog IC Placement Challenges Hierarchical and Analytical Placement Techniques for High-Performance Analog ICs Experimental Results 2

Analog Analog IC Placement IC Placement Complicated: 2-dimensional Constraints: symmetry, proximity, etc. Manual placement: low productivity and error-prone Bounding box of a placement device a symmetric group, with symmetric pairs and self- symmetric devices Analog IC placement example 4

Challenges Challenges Limitation of existing analog PDA tools: lack of designer involvement  Capture circuit design intents  Provide insurance  Spread wider use of automation tools Circuit hierarchy  Easy to read, debug and control quality Net-specific criticality  Conventional objectives of area and HPWL: insufficient for high-performance analog ICs  + Circuit performance: longer running time 5

High High-Perfor Performance mance Analog Analog IC IC Exam Example ple 1 VDD C_OUTP 0 1 fF 2 fF OUTP CLK CLK OUTN OUTP CC_OUT C_OUTN C_OUTP OUTN C_OUTN 0 1 fF 2 fF C_XP C_XN CC_XIN CC_XIP OUTP INP INN C_VG 0 -> 2 fF C_VG CLK OUTN GND Output nodes are critical => delay 6

High High-Perfor Performance mance Analog Analog IC Example IC Example 2 Current-Controlled Detects phase difference and Buffers Oscillators (CCOs) lead lag status of the 2 CCOs CCO output nodes (ring CCO oscillating nodes) are critical => CCO gain => noise shaping performance of the ring sampler 7

Prior Prior Works Works Sensitivity analysis [K. Lampaert +, JSSC’95]  Exhaustive circuit analysis was time-consuming Proximity constraints [M. Strasser +, ICCAD’08], [P. -H. Lin+, TCAD’09], [Q. Ma+, TCAD’11]  Not directly minimize the critical parasitics Monotonic current paths constraints [P.- H. Wu+, ICCAD’12], fully separation of analog and digital signal paths [P.-H. Lin+, TCAD’16]  No net-specific criticality consideration Designer-guided criticality determination + direct critical parasitic minimization are needed! 8

Our Our Contr Contributions ibutions Keep analog designers in the loop Critical parasitics to optimize circuit performance  Designer-guided  Direct critical net HPWL minimization with analytical approach Hierarchical placement  Respects multi-level hierarchical structure of analog ICs  Designer friendliness: intuitive to read and debug Hierarchical MILP and parallelization 9

Overall Overall Flow Flow Proximity Circuit Netlist Constraints Information Critical Nets Construct Circuit Hierarchical Hierarchical Structure Symmetry Constraints Hierarchical and Analytical Placement Placement Results Optimizes total area, total HPWL, and critical net HPWL 11

Cir Circuit cuit Hierarchy Hierarchy Constr Construction uction Use when the circuit hierarchy is not given Analog circuit partitioning:  Proximity groups-feasible  Symmetric groups-feasible  Critical parasitics We integrated these requirements into hMetis hMetis: http://glaros.dtc.umn.edu/gkhome/metis/hmetis/overview 12

Parallelized Parallelized Hierarchical Hierarchical Framework Framework 13

Parallelized Parallelized Hierar Hierarchical chical Framework Framework O(L) with assumptions 17

Multi Multi-Objective Objective Optimization Optimization Area, total HPWL Critical net HPWL W*H min {𝐵, 𝑋𝑀, 𝐷𝑀} min {𝑋, 𝐼, 𝑋𝑀, 𝐷𝑀} Symmetric constraints (e.g. vertical symmetric)  (symmetric pairs) 𝑦 𝑗 + 𝑥 𝑗 + 𝑦 𝑘 = 2 ∗ 𝑦 𝑡𝑧𝑛  (self-symmetric) 2 ∗ 𝑦 𝑙 + 𝑥 𝑙 = 2 ∗ 𝑦 𝑡𝑧𝑛 Non-overlapping constraints  𝑦 𝑗 + 𝑥 𝑗 ≤ 𝑦 𝑘 + 𝑋 𝑛𝑏𝑦 𝜈 𝑗𝑘 + 𝜉 𝑗𝑘 , 𝑦 𝑗 − 𝑥 𝑘 ≥ 𝑦 𝑘 − 𝑋 𝑛𝑏𝑦 (1 + 𝜈 𝑗𝑘 − 𝜉 𝑗𝑘 )  𝑧 𝑗 + ℎ 𝑗 ≤ 𝑧 𝑘 + 𝐼 𝑛𝑏𝑦 1 − 𝜈 𝑗𝑘 + 𝜉 𝑗𝑘 , 𝑧 𝑗 − ℎ 𝑗 ≥ 𝑧 𝑘 − 𝐼 𝑛𝑏𝑦 (2 − 𝜈 𝑗𝑘 − 𝜉 𝑗𝑘 ) Boundary constraints  𝑦 𝑗 +𝑥 𝑗 ≤ 𝑋, 𝑧 𝑗 +ℎ 𝑗 ≤ 𝐼 18

Handling Handling Multiple Multiple Objectives Objectives 1) Optimize H, W, WL and CL sequentially Constrain W, opt. H Constrain H, opt. W Constrain H, W, opt. WL, CL 19

Handling Handling Multiple Multiple Objectives Objectives (cont (cont.) 2) Fix maximum area and optimize WL and CL 3) Optimize weighted sum of H, W, WL and CL Example of 2) Example of 3) 20

General General MILP MILP Formulation Formulation 𝛿 : critical net weight 𝛽, 𝛾, 𝜄 : objectives weights  Optimize certain objectives by setting others to 0 𝐼 0 , 𝑋 0 , 𝑋𝑀 0 : Normalization factors  𝐼 0 , 𝑋 0 set by desired aspect ratio  𝑋𝑀 0 set to “average” total HPWL, #𝑜𝑓𝑢𝑡 ∗ (𝐼 0 + 𝑋 0 )/2 21

Cri Critical tical Parasit Parasitics ics Minimization Minimization Critical net HPWL decreases by 11.9%, total HPWL increases by 2.8% on average 23

Example Example 1: 1: Comparat Comparator Circuit or Circuit 24

Example Example 2: 2: Ring Sampler Ring Sampler Slice Slice 25

Compare Different Compare Different MOO MOO Approaches Approaches Sequential approach: best at optimizing area Fixed area approach: best at optimizing WL and CL 𝛿 = 0 𝛿 = 20 26

Comparisons Comparisons with Prior Works with Prior Works [P.- H. Lin+, TCAD’09] does not consider critical parasitics minimization Better quality with run-time overhead 27

Summary Summary Hierarchical and analytical placement techniques for high-performance analog circuits Capture design intents Directly minimize critical net HPWL Hierarchical partitioning Hierarchical MILP formulation for hierarchical placement and parallelization 28

Thanks! Thanks! Q&A 29