transactional memories a theoretical introduction
play

Transactional Memories: a theoretical introduction Selim Arsever - PowerPoint PPT Presentation

Jul 25, 2023 •213 likes •624 views

Transactional Memories: a theoretical introduction Selim Arsever & Pascal Perez Shared Memory Problems M(w,r,v) := w(f).M<w,r,f> + r<v>.M<w,r,v> A(w,r) := w<v>.WORK.r(v').[v'=v].A A<w,r> | A<w,r> |

  1. Transactional Memories: a theoretical introduction Selim Arsever & Pascal Perez

  2. Shared Memory Problems M(w,r,v) := w(f).M<w,r,f> + r<v>.M<w,r,v> A(w,r) := w<v>.WORK.r(v').[v'=v].A A<w,r> | A<w,r> | M<w,r,v> = w<v>.WORK.r(v').[v'=v].A | w<v>.WORK.r(v').[v'=v].A | w(f).M<w,r,f> + r<v>.M<w,r,v>

  3. Shared Memory Problems M(w,r,v) := w(f).M<w,r,f> + r<v>.M<w,r,v> A(w,r) := w<v>.WORK.r(v').[v'=v].A → w<a>.WORK.r(v').[v'=a].A | w<v>.WORK.r(v').[v'=v].A | w(a).M<w,r,f> + r<v>.M<w,r,v>

  4. Shared Memory Problems M(w,r,v) := w(f).M<w,r,f> + r<v>.M<w,r,v> A(w,r) := w<v>.WORK.r(v').[v'=v].A → w<a>.WORK.r(v').[v'=a].A | w<v>.WORK.r(v').[v'=v].A | w(a).M<w,r,a> + r<v>.M<w,r,v>

  5. Shared Memory Problems M(w,r,v) := w(f).M<w,r,f> + r<v>.M<w,r,v> A(w,r) := w<v>.WORK.r(v').[v'=v].A → w<a>.WORK.r(v').[v'=a].A | w<v>.WORK.r(v').[v'=v].A | w(a).M<w,r,a> + r<v>.M<w,r,v>

  6. Shared Memory Problems M(w,r,v) := w(f).M<w,r,f> + r<v>.M<w,r,v> A(w,r) := w<v>.WORK.r(v').[v'=v].A → w<a>.WORK.r(v').[v'=a].A | w<v>.WORK.r(v').[v'=v].A | w(f).M<w,r,f> + r<a>.M<w,r,a>

  7. Shared Memory Problems M(w,r,v) := w(f).M<w,r,f> + r<v>.M<w,r,v> A(w,r) := w<v>.WORK.r(v').[v'=v].A → w<a>.WORK.r(v').[v'=a].A | w<b>.WORK.r(v').[v'=b].A | w(b).M<w,r,b> + r<a>.M<w,r,a>

  8. Shared Memory Problems M(w,r,v) := w(f).M<w,r,f> + r<v>.M<w,r,v> A(w,r) := w<v>.WORK.r(v').[v'=v].A → w<a>.WORK.r(v').[v'=a].A | w<b>.WORK.r(v').[v'=b].A | w(b).M<w,r,b> + r<a>.M<w,r,a>

  9. Shared Memory Problems M(w,r,v) := w(f).M<w,r,f> + r<v>.M<w,r,v> A(w,r) := w<v>.WORK.r(v').[v'=v].A → w<a>.WORK.r(v').[v'=a].A | w<b>.WORK.r(v').[v'=b].A | w(f).M<w,r,f> + r<b>.M<w,r,b>

  10. Shared Memory Problems M(w,r,v) := w(f).M<w,r,f> + r<v>.M<w,r,v> A(w,r) := w<v>.WORK.r(v').[v'=v].A → w<a>.WORK.r(v').[b=a].A | w<b>.WORK.r(v').[v'=b].A | w(f).M<w,r,f> + r<b>.M<w,r,b>

  11. Shared Memory Problems M(w,r,v) := w(f).M<w,r,f> + r<v>.M<w,r,v> A(w,r) := w<v>.WORK.r(v').[v'=v].A → w<a>.WORK.r(v').[b=a].A | w<b>.WORK.r(v').[v'=b].A | w(f).M<w,r,f> + r<b>.M<w,r,b>

  12. Locking is dangerous ● What if a thread fails whilst holding a lock? ● Deadlocks happen! ● Linux pros on http://lwn.net/Articles/86859/

  13. Locking does not scale well Fine grained locked data structures implementation exist of the shelf but… Global knowlegde!

  14. Transaction A tomicity C onsistency I solation D urability

  15. Transaction A + B + C should remain constant under the execution of both transactions in any order. Correct: Wrong: A = A – 10 lock L 1 lock L 1 lock L 2 lock L 1 B = B – 20 A = A – 10 B = B – 20 B = B + 10 unlock L 1 unlock L 1 unlock L 2 unlock L 1 C = C + 20 B = B + 10 C = C + 20

  16. R(0) Transactional Memory W(0) W(1) R(1) W(0) A B C

  17. R(1) Transactional Memory W(0) W(1) R(1) W(0) A B C

  18. Transactional Memory Initial Situation: M T 1 n b TM T 2 T 3

  19. Transactional Memory T 1 gives his chanels to TM: M T 1 n b TM {o,g,a,c,x}

  20. Transactional Memory T 1 gets it’s copie of M: } ’ r , ’ w M’ { M T 1 n b TM {o,g,a,c,x}

  21. Transactional Memory T 1 tries to commit: } ’ r , ’ w M’ { M T 1 n b TM {o,g,a,c,x} T 2 T 3

  22. Transactional Memory A new TM is created: } ’ r , ’ w M 1 { M T 1 n b TM {o,g,a,c,x} M ’ n’’ T 2 TM’ T 3

  23. Concurrent Commit T 1 : c 1 .(c 1 + x 1 .T 1 <b>) T 2 : c 2 .(c 2 + x 2 .T 2 <b>) TM : crash | !... | k.x 1 | k.x 2 | ! p(x).k.x | c 1 .crash.n 1 ’(w’’,r’’,n’’).(TM<b,n’’>| !k | c 1 ) | c 2 .crash.n 2 ’(w’’,r’’,n’’).(TM<b,n’’>| !k | c 2 )

  24. Concurrent Commit T 1 : c 1 .(c 1 + x 1 .T 1 <b>) T 2 : c 2 .(c 2 + x 2 .T 2 <b>) TM : crash | !... | k.x 1 | k.x 2 | ! p(x).k.x | c 1 .crash.n 1 ’(w’’,r’’,n’’).(TM<b,n’’>| !k | c 1 ) | c 2 .crash.n 2 ’(w’’,r’’,n’’).(TM<b,n’’>| !k | c 2 )

  25. Concurrent Commit T 1 : c 1 .(c 1 + x 1 .T 1 <b>) T 2 : c 2 .(c 2 + x 2 .T 2 <b>) TM : crash | !... | k.x 1 | k.x 2 | ! p(x).k.x | c 1 .crash.n 1 ’(w’’,r’’,n’’).(TM<b,n’’>| !k | c 1 ) | c 2 .crash.n 2 ’(w’’,r’’,n’’).(TM<b,n’’>| !k | c 2 )

  26. Concurrent Commit T 1 : c 1 .(c 1 + x 1 .T 1 <b>) T 2 : c 2 .(c 2 + x 2 .T 2 <b>) TM : crash | !... | k.x 1 | k.x 2 | ! p(x).k.x | c 1 .crash.n 1 ’(w’’,r’’,n’’).(TM<b,n’’>| !k | c 1 ) | c 2 .crash.n 2 ’(w’’,r’’,n’’).(TM<b,n’’>| !k | c 2 )

  27. Concurrent Commit T 1 : c 1 .(c 1 + x 1 .T 1 <b>) T 2 : c 2 .(c 2 + x 2 .T 2 <b>) TM : crash | !... | k.x 1 | k.x 2 | ! p(x).k.x | c 1 .crash.n 1 ’(w’’,r’’,n’’).(TM<b,n’’>| !k | c 1 ) | c 2 .crash.n 2 ’(w’’,r’’,n’’).(TM<b,n’’>| !k | c 2 )

  28. Concurrent Commit T 1 : c 1 .(c 1 + x 1 .T 1 <b>) T 2 : c 2 .(c 2 + x 2 .T 2 <b>) TM : crash | !... | k.x 1 | k.x 2 | ! p(x).k.x | c 1 .crash.n 1 ’(w’’,r’’,n’’).(TM<b,n’’>| !k | c 1 ) | c 2 .crash.n 2 ’(w’’,r’’,n’’).(TM<b,n’’>| !k | c 2 )

  29. Concurrent Commit T 1 : c 1 .(c 1 + x 1 .T 1 <b>) T 2 : c 2 .(c 2 + x 2 .T 2 <b>) TM : crash | !... | k.x 1 | k.x 2 | ! p(x).k.x | c 1 .crash.n 1 ’(w’’,r’’,n’’).(TM<b,n’’>| !k | c 1 ) | c 2 .crash.n 2 ’(w’’,r’’,n’’).(TM<b,n’’>| !k | c 2 )

  30. Concurrent Commit T 1 : c 1 .(c 1 + x 1 .T 1 <b>) T 2 : c 2 .(c 2 + x 2 .T 2 <b>) TM : crash | !... | k.x 1 | k.x 2 | ! p(x).k.x | c 1 .crash.n 1 ’(w’’,r’’,n’’).(TM<b,n’’>| !k | c 1 ) | c 2 .crash.n 2 ’(w’’,r’’,n’’).(TM<b,n’’>| !k | c 2 )

  31. Exceptions Enhancement Avoiding Unnecessary Exceptions ● TM := (… | !p(x,cancel).(k.x + cancel)) G := … ( v cancel)(p<x,cancel>. … .(… | cancel.!k) Allowing Needed Exceptions ●

  32. Commit while Starting T 1 : c 1 .(c 1 + x 1 .T 1 <b>) T 2 : b<o 2 ,g 2 ,a 2 ,c 2 ,x 2 >.o.g … TM : crash | !... | k.x 1 | ! p(x).k.x | c 1 .crash.n 1 ’(w’’,r’’,n’’).(TM<b,n’’>| !k | c 1 ) | b(o 2 ,g 2 ,a 2 ,c 2 ,x 2 ).p<x 2 >.o …

  33. Commit while Starting T 1 : c 1 .(c 1 + x 1 .T 1 <b>) T 2 : b<o 2 ,g 2 ,a 2 ,c 2 ,x 2 >.o.g … TM : crash | !... | k.x 1 | ! p(x).k.x | c 1 .crash.n 1 ’(w’’,r’’,n’’).(TM<b,n’’>| !k | c 1 ) | b(o 2 ,g 2 ,a 2 ,c 2 ,x 2 ).p<x 2 >.o …

  34. Commit while Starting T 1 : c 1 .(c 1 + x 1 .T 1 <b>) T 2 : b<o 2 ,g 2 ,a 2 ,c 2 ,x 2 >.o.g … TM : crash | !... | k.x 1 | ! p(x).k.x | c 1 .crash.n 1 ’(w’’,r’’,n’’).(TM<b,n’’>| !k | c 1 ) | b(o 2 ,g 2 ,a 2 ,c 2 ,x 2 ).p<x 2 >.o …

  35. Commit while Starting T 1 : c 1 .(c 1 + x 1 .T 1 <b>) T 2 : b<o 2 ,g 2 ,a 2 ,c 2 ,x 2 >.o.g … TM : crash | !... | k.x 1 | ! p(x).k.x | c 1 .crash.n 1 ’(w’’,r’’,n’’).(TM<b,n’’>| !k | c 1 ) | b(o 2 ,g 2 ,a 2 ,c 2 ,x 2 ).p<x 2 >.o …

  36. Commit while Starting T 1 : c 1 .(c 1 + x 1 .T 1 <b>) T 2 : b<o 2 ,g 2 ,a 2 ,c 2 ,x 2 >.o.g … TM : crash | !... | k.x 1 | ! p(x).k.x | c 1 .crash.n 1 ’(w’’,r’’,n’’).(TM<b,n’’>| !k | c 1 ) | b(o 2 ,g 2 ,a 2 ,c 2 ,x 2 ).p<x 2 >.o …

  37. Commit while Starting T 1 : c 1 .(c 1 + x 1 .T 1 <b>) T 2 : b<o 2 ,g 2 ,a 2 ,c 2 ,x 2 >.o.g … TM : crash | !... | k.x 1 | ! p(x).k.x | c 1 .crash.n 1 ’(w’’,r’’,n’’).(TM<b,n’’>| !k | c 1 ) | b(o 2 ,g 2 ,a 2 ,c 2 ,x 2 ).p<x 2 >.o …

  38. Commit while Starting T 1 : c 1 .(c 1 + x 1 .T 1 <b>) T 2 : b<o 2 ,g 2 ,a 2 ,c 2 ,x 2 >.o.g … TM : crash | !... | k.x 1 | p(x).k.x | ! p(x).k.x | c 1 .crash.n 1 ’(w’’,r’’,n’’).(TM<b,n’’>| !k | c 1 ) | b(o 2 ,g 2 ,a 2 ,c 2 ,x 2 ).p<x 2 >.o …

  39. Commit while Starting T 1 : c 1 .(c 1 + x 1 .T 1 <b>) T 2 : b<o 2 ,g 2 ,a 2 ,c 2 ,x 2 >.o.g … TM : crash | !... | k.x 1 | p(x).k.x 2 | ! p(x).k.x | c 1 .crash.n 1 ’(w’’,r’’,n’’).(TM<b,n’’>| !k | c 1 ) | b(o 2 ,g 2 ,a 2 ,c 2 ,x 2 ).p<x 2 >.o …

  40. Commit while Starting T 1 : c 1 .(c 1 + x 1 .T 1 <b>) T 2 : b<o 2 ,g 2 ,a 2 ,c 2 ,x 2 >.o.g … TM : crash | !... | k.x 1 | p(x).k.x 2 | ! p(x).k.x | c 1 .crash.n 1 ’(w’’,r’’,n’’).(TM<b,n’’>| !k | c 1 ) | b(o 2 ,g 2 ,a 2 ,c 2 ,x 2 ).p<x 2 >.o …

Recommend

Verification of Transactional Memories that support Non-Transactional Memory Accesses Ariel Cohen

Verification of Transactional Memories that support Non-Transactional Memory Accesses Ariel Cohen

Verification of Transactional Memories that support Non-Transactional Memory Accesses Ariel Cohen 1 , Amir Pnueli 1 , and Lenore Zuck 2 1 New York University 2 University of Illinois at Chicago TRANSACT February 2008 Cohen, Pnueli, Zuck

665 views • 28 slides
Dividing Transactional Memories by Zero Aleksandar Dragojevi Rachid Guerraoui Micha

Dividing Transactional Memories by Zero Aleksandar Dragojevi Rachid Guerraoui Micha

Dividing Transactional Memories by Zero Aleksandar Dragojevi Rachid Guerraoui Micha Kapaka EPFL, Switzerland Transact 2008 Micha Kapaka (EPFL) STMBench7 Transact 2008 1 / 20 A TM Story TM implementations evaluated with skip

485 views • 27 slides
Memories Introduction Why do we need memory in an FPGA Device? Topics Types of FPGA

Memories Introduction Why do we need memory in an FPGA Device? Topics Types of FPGA

Memories Introduction Why do we need memory in an FPGA Device? Topics Types of FPGA Memories Available Resources Realizing memories in an HDL design Applications Examples Extra: Memory Controller Block Memories

692 views • 10 slides
Evaluating the Impact of Transactional Characteristics on the Performance of Transactional Memory

Evaluating the Impact of Transactional Characteristics on the Performance of Transactional Memory

Introduction Methodology Performance Evaluation Conclusions References Evaluating the Impact of Transactional Characteristics on the Performance of Transactional Memory Applications 1 Fernando Rui, 2 Mrcio Castro, 1 Dalvan Griebler, 1 Luiz

370 views • 16 slides
Memories! By: Lyndsay Smokovitz Introduction

Memories! By: Lyndsay Smokovitz Introduction

Thanks for the Memories! By: Lyndsay Smokovitz Introduction hLp://mercercogni&gt;vepsychology.pbworks.com/f/1290909633/memory.jpg Elizabeth Lo:us Cogni&gt;ve Psychologist Who? A

424 views • 11 slides
Real Time Embedded Systems &quot; Memories Memories &quot; rene.beuchat@epfl.ch LAP/ISIM/IC/EPFL

Real Time Embedded Systems &quot; Memories Memories &quot; rene.beuchat@epfl.ch LAP/ISIM/IC/EPFL

Real Time Embedded Systems &quot; Memories Memories &quot; rene.beuchat@epfl.ch LAP/ISIM/IC/EPFL Charg de cours LSN/hepia Prof. HES 1998-2008 R.Beuchat / Memories 2 General classification of electronic memories Non-volatile

1.13k views • 86 slides
A Suitcase full of memories: Exploring the meaning of tourism memories for people with dementia

A Suitcase full of memories: Exploring the meaning of tourism memories for people with dementia

A Suitcase full of memories: Exploring the meaning of tourism memories for people with dementia and their partners: reconnecting through the past. Jane Mullins (RGN, BN, PGCASR ) PhD Candidate School of Management Supervisors: Dr Diane

154 views • 14 slides
Transactional Memory 1 To read more This days papers: Herlihy and Moss, Transactional

Transactional Memory 1 To read more This days papers: Herlihy and Moss, Transactional

Transactional Memory 1 To read more This days papers: Herlihy and Moss, Transactional Memory: Architectural Support for Lock-Free Data Structures McKenney et al, Why The Grass May Not Be Greener On The Other Side: A Comparison

719 views • 41 slides
NON-BLOCKING DATA STRUCTURES AND TRANSACTIONAL MEMORY Tim Harris, 27 November 2015 Lecture 8

NON-BLOCKING DATA STRUCTURES AND TRANSACTIONAL MEMORY Tim Harris, 27 November 2015 Lecture 8

NON-BLOCKING DATA STRUCTURES AND TRANSACTIONAL MEMORY Tim Harris, 27 November 2015 Lecture 8 Problems with locks Atomic blocks and composition Hardware transactional memory Software transactional memory Transactional

1.42k views • 93 slides
NON-BLOCKING DATA STRUCTURES AND TRANSACTIONAL MEMORY Tim Harris, 25 November 2016 Lecture 8

NON-BLOCKING DATA STRUCTURES AND TRANSACTIONAL MEMORY Tim Harris, 25 November 2016 Lecture 8

NON-BLOCKING DATA STRUCTURES AND TRANSACTIONAL MEMORY Tim Harris, 25 November 2016 Lecture 8 Problems with locks Atomic blocks and composition Hardware transactional memory Software transactional memory Transactional

1k views • 89 slides
Memories and SRAM 1 Silicon Memories Why store things in silicon? Its fast!!!

Memories and SRAM 1 Silicon Memories Why store things in silicon? Its fast!!!

Memories and SRAM 1 Silicon Memories Why store things in silicon? Its fast!!! Compatible with logic devices (mostly) The main goal is to be cheap Dense -- The smaller the bits, the less area you need, and the more bits you

456 views • 21 slides
Memories and SRAM 1 Silicon Memories Why store things in silicon? Its fast!!!

Memories and SRAM 1 Silicon Memories Why store things in silicon? Its fast!!!

Memories and SRAM 1 Silicon Memories Why store things in silicon? Its fast!!! Compatible with logic devices (mostly) The main goal is to be cheap Dense -- The smaller the bits, the less area you need, and the more bits you

241 views • 22 slides
Introduction to Transactional Memory Sami Kiminki 2009-03-12 Sami Kiminki Introduction to

Introduction to Transactional Memory Sami Kiminki 2009-03-12 Sami Kiminki Introduction to

Introduction High-level programming with TM TM implementations TM in Sun Rock processor Introduction to Transactional Memory Sami Kiminki 2009-03-12 Sami Kiminki Introduction to Transactional Memory Introduction High-level programming with

682 views • 34 slides
Extending Hardware Transactional Memory to Support Non-busy Waiting and Non-transactional Actions

Extending Hardware Transactional Memory to Support Non-busy Waiting and Non-transactional Actions

Extending Hardware Transactional Memory to Support Non-busy Waiting and Non-transactional Actions Craig Zilles and Lee Baugh University of Illinois at Urbana-Champaign paper available at: http:/

453 views • 19 slides
LEAP Shared Memories: Automating the Construction of FPGA Coherent Memories Hsin-Jung Yang ,

LEAP Shared Memories: Automating the Construction of FPGA Coherent Memories Hsin-Jung Yang ,

LEAP Shared Memories: Automating the Construction of FPGA Coherent Memories Hsin-Jung Yang , Kermin E. Fleming , Michael Adler , and Joel Emer Massachusetts Institute of Technology Intel Corporation May 12th, FCCM 2014

617 views • 48 slides
Transactional Systems: Examples Core OS / RedHat: Various: SUSE: Common Properties of

Transactional Systems: Examples Core OS / RedHat: Various: SUSE: Common Properties of

Transactional Systems: Examples Core OS / RedHat: Various: SUSE: Common Properties of Transactional Systems Transactional / atomic updates Read-only root file system Focus on large deployments (clouds) or embedded systems

814 views • 36 slides
Eric Berne 1910 - 1970 Transactional Analysis UET6 TASK 02 Transactional Analysis is: A

Eric Berne 1910 - 1970 Transactional Analysis UET6 TASK 02 Transactional Analysis is: A

Eric Berne 1910 - 1970 Transactional Analysis UET6 TASK 02 Transactional Analysis is: A Extra-Freudian form of psychoanalytical theory, which examines human behaviour and communication. Not about the study of the subconsciousness, but the

417 views • 7 slides
Memories Memories Viktor wall Dept. of Electrical and Information Technology p gy Lund

Memories Memories Viktor wall Dept. of Electrical and Information Technology p gy Lund

Digital IC-konstruktion Digital IC-konstruktion Cell-phone ASIC complexity and cost Memories Memories Viktor wall Dept. of Electrical and Information Technology p gy Lund University Parts of this material was adapted from the instructor

340 views • 19 slides
Plan Hierarchical memories and their impact on our programs 1 Cache Memories, Cache Complexity

Plan Hierarchical memories and their impact on our programs 1 Cache Memories, Cache Complexity

Plan Hierarchical memories and their impact on our programs 1 Cache Memories, Cache Complexity Cache Analysis in Practice 2 Marc Moreno Maza The Ideal-Cache Model 3 University of Western Ontario, London, Ontario (Canada) Cache Complexity

632 views • 25 slides
Ego State Model Transactional Analysis Ego States P A C VISIONS Inc. Transactional Analysis

Ego State Model Transactional Analysis Ego States P A C VISIONS Inc. Transactional Analysis

Ego State Model Transactional Analysis Ego States P A C VISIONS Inc. Transactional Analysis Ego States Critic ical Parent Nurturin ring Parent Adult Adap apted d Chil ild Compliant Free Chil ild Rebellious VISIONS Inc.

409 views • 6 slides
Topic 13 Introduction to Memories and Computer Architecture Professor Peter YK Cheung Dyson

Topic 13 Introduction to Memories and Computer Architecture Professor Peter YK Cheung Dyson

Topic 13 Introduction to Memories and Computer Architecture Professor Peter YK Cheung Dyson School of Design Engineering URL: www.ee.ic.ac.uk/pcheung/teaching/DE1_EE/ E-mail: p.cheung@imperial.ac.uk PYKC 4 June 2020 Topic 13 Slide 1 DE

557 views • 18 slides
Hardware Transactional Memory Shao-Hung Chiu, Upasana Sridhar Transactional Memory - Where did

Hardware Transactional Memory Shao-Hung Chiu, Upasana Sridhar Transactional Memory - Where did

Hardware Transactional Memory Shao-Hung Chiu, Upasana Sridhar Transactional Memory - Where did we come from? Common problems in conventional lock techniques Priority Inversion: a low-priority process is preempted while holding a lock

388 views • 37 slides
Enhancing Permissiveness of Transactional Memory via Time-Warp Nuno Diegues and Paolo Romano

Enhancing Permissiveness of Transactional Memory via Time-Warp Nuno Diegues and Paolo Romano

Enhancing Permissiveness of Transactional Memory via Time-Warp Nuno Diegues and Paolo Romano ndiegues@gsd.inesc-id.pt INESC-ID/Instituto Superior T ecnico Nuno Diegues 1/17 Introduction Transactional Memory Simple API + guarantee of

719 views • 52 slides
Transactional Shipping Introduction January 2014 Shipyard Vessel Owner Lessor Bank 2

Transactional Shipping Introduction January 2014 Shipyard Vessel Owner Lessor Bank 2

Transactional Shipping Introduction January 2014 Shipyard Vessel Owner Lessor Bank 2 Acquisition Newbuilding: Shipbuilding contract 2 nd -hand tonnage: Ship purchase contract Delivery documents Registration

541 views • 24 slides

More recommend