Towards Probabilistic Timing Analysis for SDFGs on Tile Based - PowerPoint PPT Presentation

EMBEDDED REAL TIME SYSTEMS 2020 Towards Probabilistic Timing Analysis for SDFGs on Tile Based Heterogeneous MPSoCs Ralf Stemmer 1 Hai-Dang Vu 2 Kim Grüttner 3 Sébastien Le Nours 2 1 University of Oldenburg, Germany Wolfgang Nebel 1 2 University of Nantes, France Sébastien Pillement 2 3 OFFIS e.V., Germany DAAD with funds from the Federal Ministry of Education and Research (BMBF) ERTS‘20, France, 29 th January 2020 CampusFrance with funds from the French Ministry of Europe and Foreign Afgairs (MEAE) and 04.03.20 Ralf Stemmer 1 / 24 by the French Ministry for Higher Education, Research and Innovation (MESRI)

Motivation € t €€€ ? Software t €€ t 04.03.20 Ralf Stemmer 2 / 24

Approach Sofuware Hardware Models of Computation and Architecture Configuration Modeling Product Deployment Simulation Delay Annotation Analysis / DSE Hardware Sofuware Time Simulation Characterization 04.03.20 Ralf Stemmer 3 / 24

Computation Model Execution Phases t Read Compute Write A1 1 1 A0 Actor 1 A2 1 Channel Token Rate 04.03.20 Ralf Stemmer 4 / 24

Computation Model: Constraints Execution Phases t Isolated Compute Phase Read Compute Write A1 1 1 Self Scheduled A0 Actor No Interruption 1 A2 1 Channel Token Rate Blocking FIFO Bufger 04.03.20 Ralf Stemmer 5 / 24

Platform Model Execution Phases Tile 0 Tile n t Memory Memory Read Compute Write A1 FPU ... 1 1 Processing Processing Shared Element Element Memory A0 Actor 1 A2 Interconnect 1 Channel Token Rate 04.03.20 Ralf Stemmer 6 / 24

Platform Model: Constraints Execution Phases Tile 0 Tile n t Static Memory Memory Read Compute Write Local Memory RAM A1 FPU ... 1 1 Processing Processing Shared Element Element Memory A0 Actor No Caches 1 A2 Interconnect 1 1 Shared System Bus Channel Token Rate 1 Token = 1 Data Word on Bus 04.03.20 Ralf Stemmer 7 / 24

Designflow: Modeling Sofuware Hardware Shared Actors Tiles-Types Resources Configuration Modeling Product Deployment Simulation Delay Annotation Analysis / DSE Hardware Sofuware Time Simulation Characterization 04.03.20 Ralf Stemmer 8 / 24

Characterization Actors × Tile Type Tile Type A Tile Type B Channel Shared Token Rate Memory Memory Memory 1 A1 1 Channels FPU Processing Processing Element Element A0 Actor A0 A1 A2 A0 A1 A2 1 A2 1 Interconnect 04.03.20 Ralf Stemmer 9 / 24

Characterization: Computation Actors × Tile Type Tile Type A Tile Type B Channel Shared Token Rate Memory Memory Memory 1 A1 1 Channels FPU Processing Processing Element Element A0 Actor A0 A1 A2 A0 A1 A2 1 A2 1 Interconnect Actors Measurement start(); A0(&out1, &out2); Infrastructure stop(); Tiles 04.03.20 Ralf Stemmer 10 / 24 HIP3ES'17 – C. Schlaak, M. Fakih and R. Stemmer – "Power and Execution Time Measurement Methodology for SDF Applications on FPGA-based MPSoCs"

Characterization: Communication Actors × Tile Type Tile Type A Tile Type B Channel Shared Token Rate Memory Memory Memory 1 A1 1 Channels FPU Processing Processing Element Element A0 Actor A0 A1 A2 A0 A1 A2 1 A2 1 Interconnect Actors Measurement Infrastructure Tiles 04.03.20 Ralf Stemmer 11 / 24 SAMOS'19 – R. Stemmer, H.-D. Vu, K. Grüttner, S. Le Nours, W. Nebel and S. Pillement – "Experimental Evaluation of Probabilistic Execution-Time Modeling and Analysis Methods for SDF Applications on MPSoCs"

Characterization: Constraints Actors × Tile Type Tile Type A Tile Type B Channel Shared Token Rate Memory Memory Memory Dedicated 1 Interconnect A1 1 Channels FPU Processing Processing Element Element A0 Actor A0 A1 A2 A0 A1 A2 1 A2 1 Interconnect Actors On-Chip / Measurement Ofg-Chip Infrastructure Tiles 04.03.20 Ralf Stemmer 12 / 24

On-Chip Measurement On-Chip Measurement MPSoC Measurement Infrastructure 04.03.20 Ralf Stemmer 13 / 24

Ofg-Chip Measurement Ofg-Chip Measurement Measurement Infrastructure MPSoC Photo: Ralf Stemmer, 2019 04.03.20 Ralf Stemmer 14 / 24

Designflow: Characterization Sofuware Hardware Shared Actors Tiles-Types Resources Configuration Modeling Product Deployment ⚙ Measurement Infrastructure FPGA / Simulation Eval. Board Communication Analysis / DSE Model Hardware Measurements Computation Sofuware Time Model Simulation Characterization 04.03.20 Ralf Stemmer 15 / 24

Simulation Difgerent Mappings Computation Computation Models Models T0 T1 1 Interconnect A0 A1 1 ... T2 Mem. FPU Token A2 A1 Storage Actors A0 1 A2 Communication Model 1 Tiles 04.03.20 Ralf Stemmer 16 / 24

Simulation: Details Difgerent Mappings Computation Computation Models Models T0 T1 1 Interconnect A0 A1 1 ... T2 Mem. FPU Token A2 A1 Storage Actors A0 1 A2 Communication Model 1 Tiles Mappings ReadTokens(ChA) ; ReadTokens(ChA, in); wait(GetDelay(Dist A2 )) ; A2(in); 04.03.20 Ralf Stemmer 17 / 24

Designflow Sofuware Hardware Shared Actors Tiles-Types Resources Mapping / Modeling Product Configuration Deployment ⚙ Measurement Infrastructure FPGA / Simulation Evaluation Eval. Board Communication Analysis / DSE Model Hardware Measurements Computation Sofuware Time Model Simulation Characterization 04.03.20 Ralf Stemmer 18 / 24

Example: JPEG Decoder 64 64 IQ Y IDCT Y 64 64 64 64 64 64 64 64 64 64 Get 3 YCrCb IQ Cr IDCT Cr MCU RGB 64 3 3 64 64 64 64 64 IQ Cb IDCT Cb MUL FPU 04.03.20 Ralf Stemmer 19 / 24

JPEG Decoder: Characterized Actors Get OOM OOM MCU 64 64 IQ Y IQ Y IDCT Y 64 64 IQ Cr 64 64 IQ Cb 64 64 64 64 64 64 Get 3 YCrCb IQ Cr IDCT Cr MCU RGB 64 IDCT Y 3 3 64 IDCT Cr 64 64 64 64 IQ Cb IDCT Cb IDCT Cb YCrCb MUL FPU RGB Tiles MUL FPU 04.03.20 Ralf Stemmer 20 / 24

Example Hardware Shared T0 Memory Interconnect Shared T0 T1 T2 Memory MUL FPU Interconnect T0 T1 T2 T3 MUL MUL MUL Interconnect Shared T4 T5 T6 Memory 04.03.20 Ralf Stemmer 21 / 24 FPU FPU FPU

Simulative Comparison Shared T0 Avg: 2.39 · 10 6 Memory WCET: 2.77 · 10 6 Interconnect Shared T0 T1 T2 Avg: 0.94 · 10 6 Memory MUL FPU WCET: 1.19 · 10 6 Interconnect T0 T1 T2 T3 MUL MUL MUL Avg: 0.93 · 10 6 Interconnect WCET: 1.18 · 10 6 Shared T4 T5 T6 Memory 04.03.20 Ralf Stemmer 22 / 24 FPU FPU FPU

Evaluation Experiment Duration [HH:MM] WCET Error Simulation Measurement Simulation Static Math. JPEG, 1 Tile < 1 min 13:15 0.17 % 2.52 % JPEG, 3 Tiles JPEG, 3 Tile 0:39 5:13 0.05 % 7.73 % JPEG, 7 Tile 1:47 5:13 -1.52 % 7.31 % 04.03.20 Ralf Stemmer 23 / 24 ERTS‘20

Conclusion – Tiles – Caches t – Data Dependency + Characterization t + Distribution + Accuracy vs. Speed + Easy Integration t 04.03.20 Ralf Stemmer 24 / 24