Tim ing Analysis in Presence of Supply Voltage and Tem perature - PowerPoint PPT Presentation

Tim ing Analysis in Presence of Supply Voltage and Tem perature Variations Benoît Lasbouygues, Robin W ilson STMicroelectronics, Crolles France Nadine Azem ard, Philippe Maurine LI RMM, Montpellier France

Motivation Delay is strongly dependent on supply voltage + 10% Vdd, induce > + 20% delay WC/ BC drop ± 10% of V DD , is it accurate? Temperature sensitivity depends on domains Function of process and supply voltage value 15 Tim ing ( 1 2 5 ° C-m 4 0 ° C) 0 Tim ing ( 1 2 5 ° C) V DD (V) 0,8 0,9 1 1,1 1,2 ( % ) -15 -30 Tem perature I nversion Possibility to reduce m argins T. independent 2

Our goal Reduced margins using “real” V, T values for each cell Avoid over-design or re-design steps How ? Using Vdrop and T. Gradient maps Non-linear timing derating for each instance 3

How ? Manage Vdd and θ at cell level ? Popular K-factor method Voltage Temperature ∂ ∂ D D = + ∆ + θ ∆ θ Delay Do V ∂ ∂ DD V DD From a standard corner analysis we estimate timing for any Voltage and Temperature value Best case Temperature Silicon W orst case Process Voltage 4

Problem How to define accurately scaling factors? ∂ ∂ D D = + ∆ + θ ∆ θ Delay Do V ∂ ∂ DD V DD ? ? Linear function not enough accurate Polynomial template not enough accurate on large range of V DD and T. Scaling must follow physical behavior 5

Sensitivity analysis ) V / ps ( outHL V DD Derating factor must ∂ τ ∂ characterized: Slow and Fast domains Design dependence V DD ( V ) τ ( ps ) IN "0.092, 0.247, 0.553, 1.172", \ "0.093, 0.247, 0.556, 1.172", \ I nput Transition Tim e LUT "0.103, 0.258, 0.557, 1.166", \ slope "0.134, 0.275, 0.556, 1.173", \ "0.194, 0.344, 0.597, 1.176" ); Output Capacitance 6

Analytical Timing Model – Slope Modeling the transistor as a current generator C ⋅ V τ = L DD out I MAX Depending on the input range value Fast input domain: saturation current ⋅ ⋅ DW C V τ = Fast L DD ( ) α out ⋅ ⋅ − K W V V DD T Slow input domain: current function of slope 1 ⎛ ⎞ ⋅ ⋅ τ α ⋅ − α 1 + α DW C V 1 ⎜ ⎟ τ = Slow L IN DD ⎜ ⎟ α ⋅ ⋅ out ⎝ ⎠ K W 7

Analytical Timing Model – Delay Propagation Delay is strongly dependent on: Input slew Output Load Gate size I/ O coupling capacitance (Miller effect) ⎛ ⎞ ⎛ ⎞ τ α − τ 1 V 2 C ⎜ ⎟ ⎜ ⎟ = + + + IN T M out t 1 ⎜ ⎟ ⎜ ⎟ α + + ⎝ ⎠ ⎝ ⎠ 1 2 V C C 2 DD M L 8

Analytical Timing Model – Temperature Supply voltage value appears explicitly Temperature acts on Threshold Voltage and Mobility θ X ⎛ ⎞ ( ) K = − δ ⋅ θ − θ = ⋅ ⎜ ⎟ nom V V K K θ T Tnom nom nom ⎝ ⎠ ⋅ DW C τ = Fast L out θ X ⎛ ⎞ K ( ( ) ) α ⋅ ⋅ ⋅ − + δ ⋅ θ − θ ⎜ ⎟ nom K W V V θ DD T nom ⎝ ⎠ ( ) ⎛ ⎞ ⎛ ⎞ τ α − − δ ⋅ θ − θ τ 1 V 2 C ⎜ ⎟ ⎜ ⎟ = + + + in T nom M out t 1 ⎜ ⎟ ⎜ ⎟ α + + ⎝ ⎠ ⎝ ⎠ 1 2 V C C 2 DD M L 9

Derating Coefficient - V DD From analytical model, We derate formulas with respect to V DD We extract design dependency For slope in fast input domain, ( ) ∂ τ ⋅ − α ⋅ − Fast DW C 1 V V = ⋅ out L DD T + α ∂ ⋅ − 1 V K W ( V V ) DD DD T Becomes ∂ τ Fast Fast Fast a b = + Slope Slope OUT C ∂ L 2 2 V V V DD DD DD a Fast , b Fast are V DD independent parameters to be calibrated 10

Derating Coefficient – Temperature Temperature Template ∂ Fast t τ = + ⋅ = + ⋅ τ + ⋅ a b C Fast Fast Fast a b c C ∂ θ INinv INV INV L Delay Delay IN Delay L Delay ( ps) Delay ( ps) 900 C L = 1 2 0 fF C L = 1 2 0 fF 1 2 5 ° C 1 2 5 ° C 1 2 5 ° C 600 -4 0 ° C -4 0 ° C -4 0 ° C C L = 6 4 fF C L = 6 4 fF 300 C L = 4 fF C L = 4 fF I nput Slope ( ps) I nput Slope ( ps) 0 0 0 200 200 400 400 600 600 800 800 1000 1000 1200 1200 1400 1400 11

Derating Coefficient – Constraint Setup and Hold: Race between Clock and Data paths. CPN Clock C1 C2 CPI Setup = ( D1 + D2 + D3 ) – C1 CPN CPI D3 Data D1 D2 CPI CPN Ignore Load sensitivity, keep only slope variation ∂ Setup = + ⋅ τ + ⋅ τ a b c ∂ θ Setup Setup Data Setup Clock 12

Validation – Standard cell Template are fitted with 3 corners (1 ref., 1 for Vdd, 1 for T) Corner computed for an entire library with derating factor Comparison: scaling values versus electrical simulations 15 10 5 Sim ulation vs + 5 % Derating ( % ) Ref. 0 -5 0 % -10 -5 % 1.1 1 V DD ( V) 0.9 120 100 80 0.8 60 40 20 0 -20 -40 Tem perature ( ° C) 13

Application - Chip level Slope file (~ SDF) Derating on Slope 1 timing update with new slope New SDF is available (delay can be Com pute delay scaled using internal developed tool) W ith new slope Final annotation is done Final SDF Derating on Delay 14

Application – Chip level Chip Vdrop map Timing Analysis with Vdrop data From a worst case corner, we update delay with Vdrop maps. We compute each Slope and Delay derating (cell by cell) IP Vdrop map Comparison : TA with (Vdd – 10% ) Versus : TA with Vdrop Data 15

Results Comparison Spice/ WC/ Derating Margin gain : 9 to 12% ~ 200ps Path Delay ( ns) 2 ,5 0 1 2 % 9 % 2 ,2 5 2 ,0 0 W orst case tim ing 2 % accuracy Derating analysis 1 ,7 5 Spice analysis 0 1 2 3 4 5 6 7 8 Path # 16

Summary We propose a method to handle Temperature/ V DD variations based on cell by cell scaling factor These deratings are non-linear and function of design conditions Taking account Vdrop in TA, highlights a significant gain in margin versus standard worst case method. Voltage Derating could be also used to validate Dynamic Voltage, Multi-Voltage feature Method has demonstrated for precise Temperature effects such as Temperature inversion and can be used to characterize hot spots. 17

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