The Time-predictable Multicore Architecture T-CREST Martin Schoeberl Technical University of Denmark
New Architectures Needed n Design a computer architecture for real-time systems t Worst-case execution time (WCET) is the main design constraint t Average-case performance not (so) interesting n Use and develop features that are t WCET analysis driven t Have a low WCET Martin Schoeberl T-CREST 2
Time-predictable Computer Architecture n Common computer architecture wisdom Make the common case fast and the uncommon case just correct n Time-predictable computer architecture Make the worst case fast and the whole system analyzable Martin Schoeberl T-CREST 3
T-CREST Architecture n Chip-multiprocessor for high performance t Target: 64 cores in an FPGA n Time-predictable t Processor t Network-on-Chip (NoC) t Local memory (SPM, $) t SDRAM controller n Integration in WCET analysis n Compiler support for WCET analysis Martin Schoeberl T-CREST 4
T-CREST Outcome n Provide a complete platform t Hardware in an FPGA t Supporting compiler and analysis tool n Resulting designs in open source t BSD license t Simplifies cooperation n Up to compiler t No operating system research t No Model of Computation research t No automatic parallelization research Martin Schoeberl T-CREST 5
Platform - Hardware R R R NI NI NI Patmos Patmos Patmos SPM SPM SPM + + + M$ Dec M$ Dec M$ Dec S/D$ S/D$ S/D$ Memory Tree Memory T-CREST Chip Controller SDRAM Memory Martin Schoeberl T-CREST 6
Platform - Software Martin Schoeberl T-CREST 7
T-CREST Partners Martin Schoeberl T-CREST 8
Processor n Time-predictable processor t Written in Chisel n Called Patmos n Flexibility to define the instruction set t A compiler is adapted for Patmos at TUV n Co-design for low WCET of t Patmos t Compiler t WCET analysis Martin Schoeberl T-CREST 9
Patmos n A research platform for real-time architecture (e.g. caches, SPM) n RISC style microprocessor n Dual issue VLIW n Full predication – all instructions n Split caches t Scratchpad memory (SPM) t Stack cache t Data cache t Method cache Martin Schoeberl T-CREST 10
Pipeline Overview Fetch Decode Execute Memory Writeback M$ RF RF + S$ + PC IR Dec D$ SP Martin Schoeberl T-CREST 11
Patmos WCET Features n No timing anomaly t As far as I know ;-) n Constant execution time of instructions n 0 timing dependency between instructions t All caches miss in the same pipeline stage t Load/use dependency scheduled by the compiler Martin Schoeberl T-CREST 12
Compiler n Adaption of LLVM n Full support of Patmos ISA n Support for stack cache instructions t Reserve, free, ensure n Support for method cache n Optimize for WCET t Integration with AbsInt aiT tool t Delivers flow facts for aiT t Single-path code generation Martin Schoeberl T-CREST 13
Network on Chip (NoC) n Two types of traffic: t Processor to processor • DMA driven block transfers SPM → SPM (message passing) • Nature: All-to-all t Processor to shared memory (SDRAM) • Arbitration in NOC and in memory controller • Nature: All-towards-one n Globally-Asynchronous Locally-Synchronous (GALS) implementation of platform Martin Schoeberl T-CREST 14
NoC Centric View Clock domain CPU CPU CPU $ SPM $ $ SPM SPM Read/write memory-style interface NI NI NI The NOC Clock domain Mesochronous NIs NI NI NI Asynchronous - Packet switched - TDM based CPU CPU CPU $ $ SPM SPM $ SPM Martin Schoeberl T-CREST 15
Real-Time Guarantees n NoC is a shared communication medium n Needs arbitration t Time-division-multiplexing is predictable n Message latency/bandwidth depends on t Schedule t Topology t Number of nodes Martin Schoeberl T-CREST 16
Argo – the T-CREST NoC n TDM based NoC – statically scheduled n Different packet sizes possible n 3 stage pipelined router t Synchronous and asynchronous n Network interface (NI) t Ticks at TDM clock (mesochronous) • Drives the asynchronous network t Time shared DMA machinery t SPM for clock domain crossing Martin Schoeberl T-CREST 17
A TDM-based Router Link HPU Link HPU Link Link X bar . . . . . . . . . . . . Link HPU Link Payload Header R oute flit flit Martin Schoeberl T-CREST 18
Network Interface for Argo Traditional NI design Argo micro-architecture Martin Schoeberl T-CREST 19
Argo NI Key Features n SPM used for clock domain crossing n One DMA needed per connection n But only one active at any given time due to TDM t Enables efficient table-based implementation of DMA controllers n End-to-end (i.e., SPM-to-SPM) data transfer t Avoids buffering and flow control Martin Schoeberl T-CREST 20
Distributed TDM Memory NoC Processor Processor Processor Processor core core core core OCP NI NI NI NI MI OCP Memory controller Multicore Memory Martin Schoeberl T-CREST 21
TDM Tree n The TDM schedule at the memory interface t No buffering in the memory controller n Pipelined tree and response channel n Pipeline delay in tree is known t No buffering in tree nodes n Distributed TDM arbitration at nodes t Just with the right offset t The packet knows when to go Martin Schoeberl T-CREST 22
WCET Analysis n Adaption of AbsInt aiT tool n Support of Patmos ISA t Predicated instructions t Dual-issue pipeline n Simple method cache analysis n Stack cache analysis n Integration with compiler t platin Martin Schoeberl T-CREST 23
Software and Tools n Operating systems (single core) t RTEMS t ARINC 653 OSPAT n Operating system multi-core t MOSSCA from Augsburg n NoC schedule generator n NoC user library n Two use cases from industry partners for platform evaluation Martin Schoeberl T-CREST 24
Using T-CREST n Open source t Industry friendly BSD license n Hosted at GitHub t https://github.com/t-crest t You can join the team and get write access n Only (mostly) free tools used n Public mailing list patmos-processor at Yahoo n http://patmos.compute.dtu.dk/ Martin Schoeberl T-CREST 25
FPGA Platforms Martin Schoeberl T-CREST 26
Simulation (SW) n Processor simulation t SW simulator t HW based emulator n LLVM compiler n Just your laptop Martin Schoeberl T-CREST 27
Simulation (HW) n Processor simulation t HW based emulator t Free wave viewer n Multicore simulation t ModelSim, license for multi language Martin Schoeberl T-CREST 28
The Real Thing - Hardware n Full T-CREST execution t 9 cores n On $ 300 FPGA board n Only free tools needed Martin Schoeberl T-CREST 29
Future Work n EC project finished t Continue with DK funded project PREDICT n We will keep the T-CREST name n Platform for future EC funded projects n Immediate next steps t Programming models t Full system simulator (C++) t Integration with SWEET (platin) Martin Schoeberl T-CREST 30
The T-CREST Team Martin Schoeberl T-CREST 31
Want to Learn at SYCHRON n How to program T-CREST n We need a programming model t That includes computation and communication n Maybe synchronous languages would fit n Support for multicore processor t Using message passing NoC n Let’s team up Martin Schoeberl T-CREST 32
Summary n We need new computer architecture for real-time systems n WCET analyzability is of primary importance n T-CREST is a platform t Processor, NoC, memory controller, compiler, WCET analysis n Technology is mostly open source n https://github.com/t-crest Martin Schoeberl T-CREST 33
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