SLIDE 1
The Advanced Implantation Detector Array (AIDA) Robert Page The - - PowerPoint PPT Presentation
The Advanced Implantation Detector Array (AIDA) Robert Page The - - PowerPoint PPT Presentation
The Advanced Implantation Detector Array (AIDA) Robert Page The AIDA Project Funded by UK EPSRC/STFC (~2M) Collaboration between University of Liverpool University of Liverpool University of Edinburgh STFC Daresbury Laboratory STFC
SLIDE 2
SLIDE 3
FAIR context
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Super FRS
Advanced Implantation Detector Array (AIDA) DEcay SPECtroscopy (DESPEC)
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FRS vs. Super FRS
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Predicted Super FRS Yields @ 1012/s
c number Z → Neutron number N → Atomic nu
= 3.6 / hour = 0.6 / week
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A & Z separation
Isomer γ decays for unique A & Z identification
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Experimental concept
ion beam
AIDA
3He proportional counters
β decay
n
AIDA
Moderator block (polyethylene)
3He proportional counters
Side view Front view
Moderator block (polyethylene)
n
Segmented Si detector (DSSD) for ion-β correlations
SLIDE 9
Predicted Super FRS Yields @ 1012/s
c number Z → Neutron number N → Atomic nu
= 3.6 / hour = 0.6 / week
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AIDA design – some criteria
- 1. Highly segmented for reliable ion-β correlations at high rates
- 2. Low energy threshold (50 keV) for high β detection efficiency
- 3. Large energy range to measure ion energies (20 GeV) too!!
- 4. Many Si planes to stop all ions (~10 mm thickness)
- 5. Active area to cover (Super) FRS focal plane or single nuclide
- 6. Compact to fit inside neutron array, RISING Ge array, …
- 7. Minimum material – n, γ absorption/scattering
- 8. Good time resolution for n time of flight, …
- 9. Measure decays within ~µs of ion implantation!
- 10. Spectroscopic performance for decays
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AIDA Design
“standard” configuration “compact” configuration 24 cm x 8 cm 8 cm x 8 cm
Si thickness = 1 mm, strip pitch = 625 µm, >5000 channels
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Compatibility with neutron array
BELEN
28 → 44
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Compact configuration
DSSDs ASICs + FEE cards
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Compatibility with RISING
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Compatibility with future Ge array
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AIDA ASIC Design
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AIDA ASIC Design
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AIDA ASIC
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AIDA ASIC & readout
Mezzanine card: 4x 16 channel ASICs Cu cover EMI/RFI/light screen cooling
FEE card: 4x 16-bit ADC MUX readout (not visible) 8x octal 50MSPS 14-bit ADCs Xilinx Virtex 5 FPGA PowerPC 40x CPU core – Linux - MIDAS
Gbit ethernet, clock, JTAG ports, power
FEE card width: 8cm Prototype – air cooling Production – recirculating coolant
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Packaged AIDA FEE cards
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AIDA clock box
Master SYNC to clock box
FEE64 FEE64 FEE64
Clock box
200MHz clock and SYNC distribution
For operating >1 AIDA FEE64 Module may be cascaded
FEE64 (sync master)
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Commissioning experiments
TAMU – β-delayed proton emitters – MARS GSI – α emitters with N~126 GSI – α emitters with N~126 (219-223U, 218-221Pa, 216-220Th)
- r 109I & 106Te
– FRS
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Status Summary
Mechanical assembly of prototype complete Thermal tests of DSSD cooling ongoing Bench tests of ASICs, FEE cards ongoing pulsers → electron sources pulsers → electron sources Commissioning experiments soon (?) First experimental proposals to GSI PAC
Further information: http://www.ph.ed.ac.uk/~td/AIDA
SLIDE 24
Collaborators
R.D. Page, T. Grahn, University of
- S. Rinta-Antila, D.A. Seddon
Liverpool
- T. Davinson, Z.Liu,
University of P.J. Woods Edinburgh P.J. Woods Edinburgh P.J. Coleman-Smith, I.H. Lazarus, STFC S.C. Letts, P. Morrall, V.F.E. Pucknell, Daresbury
- J. Simpson, J. Strachan
Laboratory
- D. Braga, M. Prydderch, S.L. Thomas