T erna ry and Quaterna ry Lattice Diagrams Singapur, Septemb er 1997 1 ' $ TERNARY AND QUA TERNARY LA TTICE DIA GRAMS F OR LINEARL Y-INDEPENDENT LOGIC, MUL TIPLE-V ALUED LOGIC, AND ANALOG SYNTHESIS Ma rek A. P erk o wski, Edmund Pierzchal a, and Rolf Drechsler +, Dept. Electr. Engn., P o rtland State Universit y , P o rtland, USA + Inst. Comp. Sci., Alb ert-Ludwigs-Universit y , F reiburg in Breisgau, Germany & %
T erna ry and Quaterna ry Lattice Diagrams Singapur, Septemb er 1997 2 ' $ PLAN Intro duction - la y out-driven synthesis. � Expansions and expansion no des. � Max-t yp e versus LI-t yp e lattices. � Bina ry LI-t yp e lattices. � T erna ry lattices. � Quaterna ry lattices. � Butter�y algo rithm to �nd b est expansions. � Applicati ons to F uzzy and analog circuits. � & %
T erna ry and Quaterna ry Lattice Diagrams Singapur, Septemb er 1997 3 ' $ LA TTICE DIA GRAMS. Review Bina ry Lattice Diagrams . � Intro duce T erna ry and Quaterna ry Lattice Diagrams . � Such diagrams a re applica bl e to submicron design and designing � new �ne-grain digital, analog and mixed FPGAs. Diagrams p resented here expand the ideas of Lattice diagrams � (P erk o wski, Jesk e) and Linea rly Indep endent (LI) Logic (P erk o wski, F alk o wski, Beyl, Sa rabi). & %
T erna ry and Quaterna ry Lattice Diagrams Singapur, Septemb er 1997 4 ' $ THE GO AL OF LA TTICE DIA GRAMS The goal of Lattice Diagrams is la y out-dri ven logic synthesis � in cellula r structures with mostly lo cal connections. The concept of a lattice diagram involves three comp onents: � (1) expansion of a function (the function co rresp onds to the initial no de in the lattice), which creates several successo r no des of this no de, (2) joining of several (not necessa rily tautologic) no des of a tree level to a single no de, which is in a sense a reverse op eration to the expansion, (3) a regula r geometry to which the no des a re mapp ed, this geometry guides which no des of the level a re to b e joined. & %
T erna ry and Quaterna ry Lattice Diagrams Singapur, Septemb er 1997 5 ' $ REGULAR LA YOUT GEOMETRY FROM LA TTICE DIA GRAMS In a regula r la y out, every cell is connected to 4 (bina ry lattice), 6 � (terna ry lattice) o r 8 (quaterna ry lattice) neighb o rs and to a numb er of vertical, ho rizontal and diagonal buses. Cell with inputs and outputs is said to have x � n m n m connectivit y pattern . T erna ry lattices have 3 inputs and 3 outputs from a no de. � Quaterna ry lattices have 4x4 connectivit y pattern, it means, 4 � inputs and 4 outputs from a no de. & %
T erna ry and Quaterna ry Lattice Diagrams Singapur, Septemb er 1997 6 ' $ REGULAR LA YOUT GEOMETRY FROM LA TTICE DIA GRAMS. I I Expansions a re: Shannon, Davio, nonsingula r, fuzzy and analog. � F o r each t yp e of expansion on no des, there exists t yp e of � joining op eration fo r no des. The p ro cedure of building the lattice diagram, i.e. the la y out of a � function, consist in expanding and joining no des in levels iteratively fo r (rep eated) va riables until all no de functions b ecome va riables o r constants. & %
T erna ry and Quaterna ry Lattice Diagrams Singapur, Septemb er 1997 7 ' $ EXP ANSION NODES F OR BINARY, MUL TI-V ALUED AND FUZZY FUNCTIONS d a a (a) (b) b d c b S a 0 d a (c) 1 d b c c 0 1 a b c 3 (e) literal 1 a b MIN d b2 b 3 (d) c d a 3 MAX 4 bb2 literal 2 a MIN (f) d b3 4 c c 4 a literal 1 b a MIN (g) 2 b2 b d b3 MAX d literal 2 a MIN 4 4 b2 (h) 2 c literal a MIN 3 c & %
T erna ry and Quaterna ry Lattice Diagrams Singapur, Septemb er 1997 8 ' $ SHANNON EXP ANSION NODES. d a (a) b S a 0 d 1 c 0 1 b c Shannon (S) expansion: a multiplexer, and a general notation of a 2x2 cell in � a Lattice. When input is inverted, the so-called Reversed Shannon (S') expansion is � a executed, which means that the role of inputs and is reversed. b c & %
T erna ry and Quaterna ry Lattice Diagrams Singapur, Septemb er 1997 9 ' $ D A VIO EXP ANSION NODES. a (b) b d c a (c) d b c a (b) sho ws the p ositive Davio expansion no de (pD), and (c) the negative Davio � no de (nD). Such no des a re used in P ositive-P ola rit y , Fixed-P ola rit y , Kroneck er and � Pseudo-Kroneck e r Lattices and their generalizations. & %
T erna ry and Quaterna ry Lattice Diagrams Singapur, Septemb er 1997 10 ' $ MUL TI-V ALUED EXP ANSION NODES. a a 3 (e) b b d b2 (g) 2 b2 3 c 3 b3 a d 4 4 bb2 (f) 4 d b3 2 4 c c 4 (e) p resents Shannon no de fo r terna ry logic, (f ) Shannon no de fo r quaterna ry � logic, and (g) realization of the quaterna ry Shannon no de from (f ) in bina ry logic. Tw o bina ry signals routed together simulate a 4-valued signal. � & %
T erna ry and Quaterna ry Lattice Diagrams Singapur, Septemb er 1997 11 ' $ FUZZY LOGIC EXP ANSION NODES. literal 1 literal 1 a a MIN MIN b b (d) d d MAX MAX literal 2 literal 2 a a MIN MIN b2 c (h) literal a MIN 3 c (d) DFL (Disjoint F uzzy Logic) with 2 literals. (h) DFL with 3 literals. & %
T erna ry and Quaterna ry Lattice Diagrams Singapur, Septemb er 1997 12 ' $ EXISTENCE OF JOINING OPERA TIONS AS A CONDITION OF BUILDING LA TTICES W e denote max-t yp e op erations b y + , min-t yp e op erations b y � . � It can b e observed, that a fundamen tal condition fo r existence of � joining op erations is that in the underlying algeb raic structure any t w o literals a re disjoint. In bina ry , this p rop ert y reduces to 0 . � = � a � a Existence of joining op erations is the condition of b eing able to � create lattice diagrams. This condition leads to bina ry and multiple-valu ed (MV) Max-t yp e � lattices. The p rinciple of op eration of bina ry max-t yp e lattices is that any � path in a diagram that includes and cancells . � x x & %
T erna ry and Quaterna ry Lattice Diagrams Singapur, Septemb er 1997 13 ' $ EXISTENCE OF JOINING OPERA TIONS F OR LI-TYPE LOGIC � EX OR function is: = b . + � � a � b a � b a � Thus, = 0 . � + � = � a � a a a a a This leads to Linea rly-Indep en den t t yp e (LI) lattices. � The p rinciple of op eration of LI-t yp e lattices is that any t w o � identical paths to the ro ot in the diagram cancel one another ( x 0 ). = � x & %
T erna ry and Quaterna ry Lattice Diagrams Singapur, Septemb er 1997 14 ' $ COMP ARISON OF THREE TYPES OF LA TTICES F OR TW O-OUTPUT EX OR/XNOR FUNCTION exor xnor(a,b,c,d) exor(a,b,c,d) exor xnor(a,b,c,d) a a s s a s s’ 1 pD 1 xnor(a,b,c,d) 0 0 0 1 0 1 b b s s s s s’ b pD pD 1 1 a 1 0 0 0 0 1 1 0 c c s s s s s s’ c pD 1 1 0 1 0 1 0 1 1 0 0 0 d s s s s s s s’ d d pD 1 0 1 1 1 1 1 1 0 0 0 0 0 0 1 1 0 1 0 0 0 1 0 (a) (c) (b) (a) 2x2 lattice with S, (b) 3x3 lattice with S and S', (c) 2x2 lattice with pD and pD'. & %
T erna ry and Quaterna ry Lattice Diagrams Singapur, Septemb er 1997 15 ' $ CREA TION OF A POSITIVE D A VIO LEVEL IN A LA TTICE (a) g f h (c) g h pD pD pD a a 1 1 a 1 a 1 a g2 h h pD g0 2 pD pD 0 1 1 b 1 b b join(g , h ) 1 nD 2 0 nD nD c 1 (b) 1 c g h pD’ pD’ a 1 1 a a 1 h + g2 g + a h a g + h d 2 0 0 0 2 cancel for h cancel for g (a) t w o expanded no des b efo re joining, (b) la y er of lattice after Figure 1: joining op eration on no des and , (c) Fixed-P ola rit y RM Lattice fo r g h 2 0 functions h . f ; g ; & %
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