Systems Delays Shankar Balachandran* Associate Professor, CSE - PowerPoint PPT Presentation

Spring 2015 Week 5 Module 24 Digital Circuits and Systems Delays Shankar Balachandran* Associate Professor, CSE Department Indian Institute of Technology Madras *Currently a Visiting Professor at IIT Bombay

RC Delay Model  Use equivalent circuit for transistors  Ideal switch + capacitance and ON resistance  Unit nMOS has resistance R, capacitance C  Unit pMOS has resistance 2R, capacitance C  Capacitance proportional to width  Resistance inversely proportional to width Delays 2

Inverter Delay = 6RC Delays 3

Timing Parameters  Rise Time ( t r ), the time required for a signal to transition from 10% of its maximum value to 90% of its maximum value.  Fall Time ( t f ), the time required for a signal to transition from 90% of its maximum value to 10% of its maximum value.  Propagation Delay ( t pLH , t pHL ), the delay measured from the time the input is at 50% of its full swing value to the time the output reaches its 50% value. Delays 4

Timing parameters (contd…) V in V max 0.5 V max 0 time t pLH t pHL V out V max 0.9 V max 0.5 V max 0.1 V max 0 time t r t f • Gate delays and the corresponding waveform representation capture the dynamic behavior of a circuit. The propagation path that determines the delay through the circuit is called the critical path . Delays 5

Timing Analysis of Combinational Circuits  Using gates with finite propagation delays, t pLH and t pHL instead of zero gate delays used in functional analysis. t pLH t pHL Gate INV 3 ns 2 ns XOR 5 ns 4 ns Delays 6

0 → 1 Transition on V in V in V 1 2 Gate t pLH t pHL V 2 3 INV 3 ns 2 ns XOR 5 ns 4 ns V 3 2 5 V out 4 8 ns t=0 1 → 0 Transition on V in V in V 1 3 V 2 2 V 3 3 5 V out 4 9 ns Delays 7

Example: Gate delay  Determine the worst case propagation delay through these circuits. 2 gd 4 ns 2 ns 5 gd    t 2 4 6 ns p 3 gd             t max 2 5 , 3 5 , 3 8 gd 3 gd 6 gd p 2 gd 5 gd 3 gd                t max 2 5 , 3 5 , 3 , 6 3 9 gd p Delays 8

Gate Delay Reality!  The time delay of a gate is affected by the following:  Intrinsic delay of the gate, i.e., delay due to internal load.  Fanout (load) dependent delay. Delay of a gate increases as its fanout (capacitive load in CMOS) increases.  Fanin dependent delay. Gates with high fanin have high delay.  Supply voltage fluctuations affect delay. Delay decreases with increase in supply voltage ( to some extent only !).  Simple gate delay model for CMOS gates:   t t t C p int load load total load (fF) = intrinsic delay (ns) capacitive load due fanout gates + interconnecting wires load dependent delay (ns/fF) Delays 9

Gate Delay Example: c 1 Input Delay t p (ns) Gate Cap. (fF) C L in fF a b d NOT 10 0.05 + 0.017 C L AND2 15 0.15 + 0.037 C L AND3 20 0.20 + 0.038 C L 2 OR2 15 0.20 + 0.019 C L 3 4 5 OR3 20 0.34 + 0.022 C L 6 7 Assume a fanout of 4 NOTs load at each output. z   x       t 0.05 0.017 2 15 2 20 1.24 ns 1      t 0.15 0.037 15 0.705 ns 2         t t t 1.665 ns t t t 2.5 ns    t 0.34 0.022 20 0.78 ns   a x 2 6 a z 4 7 3         t t t 1.665 ns t t t 2.5 ns    t 0.34 0.022 20 0.78 ns   b x 2 6 b z 3 7 4              t t t 2.115 ns t max t t , max t t , t 3.74 ns    t 0.20 0.019 20 0.58 ns   c x 1 6 c z 4 1 3 5 7 5            t 0.20 0.019 4 10 0.96 ns t max t t , t 2. 5 n s 6  d z 4 5 7           t 0.20 0.038 4 10 1.72 ns critical paths: c z t 3. 4 7 ns 7 p Delays 10

End of Week 5: Module 24 Thank You Delays 11