SiP Technology and Testing Name: Philippe Cauvet Date: 2007, March 28
Outline • Definition • Market / Applications • Design and technology • Packaging Technologies • Test Challenges • Conclusion 2 Journée EEA Montpellier Philippe Cauvet, Mar 28, 2007
What is a SiP? System-in-package (SiP) = any combination of semiconductors, passives, and interconnects integrated into a single package SiP (System-in-Package) is a functional system or subsystem assembled into a single package 3 Journée EEA Montpellier Philippe Cauvet, Mar 28, 2007
Outline • Definition • Market / Applications • Design and technology • Packaging Technologies • Test Challenges • Conclusion 4 Journée EEA Montpellier Philippe Cauvet, Mar 28, 2007
Market Trends Why a slowdown ? Industry moves to SiP Missing CAD tools certainly an obstacle Source: Gartner 1Q06 SiP Market Projection 12 000 12 000 10 000 10 000 CAGR 04-10 10% 8 000 8 000 Automotive Mu Shipment Communications 6 000 6 000 Consumer Data Processing Industrial 4 000 4 000 2 000 2 000 0 0 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 � Gartner updates every quarter its SiP Market Projection � Gartner view slightly increased since 3Q04 with 10% CAGR 04-09 compared to 5% CAGR 04-09 for Semiconductors: SiP and SoC grow in parallel! � Gartner sees as much SiP in Consumer as Communication 5 Journée EEA Montpellier Philippe Cauvet, Mar 28, 2007
Applications Leading Applications for SiPs • Applications include portable consumer products such as digital camcorders and cameras • Mobile phone is the volume driver – Logic and memory combo – Digital baseband section – Transceiver section – RF section 6 Journée EEA Montpellier Philippe Cauvet, Mar 28, 2007
Applications: DSC SiPs show up in portable devices 7 Journée EEA Montpellier Philippe Cauvet, Mar 28, 2007
8 Philippe Cauvet, Mar 28, 2007 Journée EEA Montpellier Applications: Mobile phones
9 Philippe Cauvet, Mar 28, 2007 Journée EEA Montpellier Applications: Bluetooth TM Bluetooth Radio: >1Billion Units shipped in 2006
Applications: OneChipSTB One board PCB One board PCB 2 layers 2 layers EEPROM EEPROM 16Mb 16Mb 16Kb 16Kb SDRAM SDRAM 16 16 I²C I²C CVBS CVBS Analogue video Analogue video RF input RF input SVHS SVHS Tuner Tuner Channel Channel One package STB One package STB CINCH CINCH Audio Audio sbSIP + technology sbSIP + technology Right Right I²S I²S DAC DAC Front panel Front panel CINCH CINCH Left Left Bi-colour LED and Bi-colour LED and IrDA Receiver IrDA Receiver ISO7816 ISO7816 16 16 MPEG2 MPEG2 Smart Smart UARTs UARTs 4Mb 4Mb Card(s) Card(s) FLASH FLASH Video & Audio Video & Audio Decoder Decoder 9.43 9.43 9.43 mm mm mm Pics die 268 wires Pics die 268 wires Pics die 268 wires 64.4 mm² 64.4 mm² 64.4 mm² Silicon Silicon Silicon Silicon Tuner die Tuner die Tuner die TDA8262 TDA8262 TDA8262 Tuner Tuner Tuner Tuner 50 bumps 50 bumps 50 bumps 4.9mm² - 0.58W 4.9mm² - 0.58W 4.9mm² - 0.58W MOJO die MOJO die MOJO die MPEG2 MPEG2 MPEG2 MPEG2 6.83 6.83 6.83 mm mm mm PNX8316 PNX8316 PNX8316 A/V decoder A/V decoder A/V decoder A/V decoder Channel die Channel die Channel die 292 bumps 292 bumps 292 bumps Channel Channel Channel Channel TDA10086 TDA10086 TDA10086 20.4mm² - 20.4mm² - 20.4mm² - 72 bumps 72 bumps 72 bumps decoder decoder decoder decoder 7.4mm² - 0.76W 7.4mm² - 0.76W 7.4mm² - 0.76W 1W 1W 1W (drawing not to scale) (drawing not to scale) (drawing not to scale) BGA292 BGA292 BGA292 10 Journée EEA Montpellier Philippe Cauvet, Mar 28, 2007
Outline • Definition • Market / Applications • Design and technology • Packaging Technologies • Test Challenges • Conclusion 11 Journée EEA Montpellier Philippe Cauvet, Mar 28, 2007
SiP vs SoC (1) Single piece of silicon SoC Single technology Single level of interconnection Multiple chips Multiple technologies SiP Multiple levels of interconnection… …and 3D 12 Journée EEA Montpellier Philippe Cauvet, Mar 28, 2007
SiP vs SoC (2) Low High Production Volume Simple High Factors to Consider: Favor the use of SoC. � Production Volume Consider Factors � Design Environment Carefully. � Dev Cost (Incl. IP Cost) � Reliability � Die Maturity � Technologies (RF, Memories…) Technical Performance / Mix Speed + Favor the use of SiP. Consider Factors Market Environment Carefully. Complex Low Source: Gartner 2006 Contibutor: JM Yannou, NXP SiP Time to Market Innovation Manager Short Long 13 Journée EEA Montpellier Philippe Cauvet, Mar 28, 2007
Focus on EMC (and SiP): new challenges non SiP system SiP Components placement is done at the Components placement is done same time as circuits design: empirically after circuits design predictability needed! ? system goes 3D! + components are closer to each other! ? 14 Journée EEA Montpellier Philippe Cauvet, Mar 28, 2007
Example of an inter-system (inter SiP in susceptibility) EMC challenge Digital IC TV: TV: up to 862MHz up to 862MHz GSM: GSM: from 890MHz on from 890MHz on The GSM antenna emits Decoupling capacitors signals considered as Analog IC integrated in silicon (Philips noise by the close-by PICS technology), flip-chip low-amplitude bumped on digital: -16dB large-bandwidth TV RF noise reduction measured! receiving subsystem 15 Journée EEA Montpellier Philippe Cauvet, Mar 28, 2007
Outline • Definition • Market / Applications • Design and technology • Packaging Technologies • Test Challenges • Conclusion 16 Journée EEA Montpellier Philippe Cauvet, Mar 28, 2007
SiP vs SoC 17 Journée EEA Montpellier Philippe Cauvet, Mar 28, 2007
Packaging challenges • Higher integration requires smaller chips, with smaller pad pitch and size • More chips = thinner chips (how to handle <100µm wafers?) • More functionalities = more power • Cost of materials 18 Journée EEA Montpellier Philippe Cauvet, Mar 28, 2007
19 Philippe Cauvet, Mar 28, 2007 Journée EEA Montpellier Source: STATSChippac Packaging
20 Philippe Cauvet, Mar 28, 2007 Journée EEA Montpellier Source: DPC Packaging
Packaging Intel Package-on-Package construction (folded flex circuit from Tessera) Processor, flash & SDRAM – Prototype of 8-dies stack with no interposer (50µm die thickness) Intel is now using copper pillar bumping for its processors 21 Journée EEA Montpellier 15 Philippe Cauvet, Mar 28, 2007
Packaging Tessera Carrier R L (Q) C Interconnectivity Flex no 60 no 14 lines/mm Si/GaAs no ? 0,11nF/mm² ? Package-on-Package (folded carrier) – 2 metal-layer polymide providing electrical and mechanical properties for interconnect Processor with associated memory Tessera/Intel folded stacked CSP package Configuration examples Folded Stacked CSP assembly process Sources : Prismark wireless technology report – March 2005 22 Journée EEA Montpellier Philippe Cauvet, Mar 28, 2007
Packaging MMM6000 Module Freescale Single package transceiver for quad band EGPRS (GSM/GPRS/EDGE) – 11.2x9mm – 9 SMDs 0402 – 18 SMDs 0201 – 2.8x2.6mm 0.13µm CMOS – 2.7x2.9mm 0.18µm RFCMOS – 1.1x1.1mm IPD device 23 Journée EEA Montpellier Philippe Cauvet, Mar 28, 2007
Packaging Sychip Silicon substrate with integrated passives Size (mm) 9x9 I/O 12x12 Availability Sampling? Known Partnerships ? Source : Sychip 24 Journée EEA Montpellier Philippe Cauvet, Mar 28, 2007
Packaging NXP Silicon-based SiP Standard concept HVQFN package Flip chip Passive die Molding compound Passive die Active die tip tip lead lead Key benefits • Performance (flip chip interconnects) Flip chip � Inductance / 4 to 6! Active die • Size (3D stacking, passive integration) • Low thermal resistance 25 Journée EEA Montpellier Philippe Cauvet, Mar 28, 2007
26 Philippe Cauvet, Mar 28, 2007 Journée EEA Montpellier MEMS Packaging
MEMS packaging SAW filter on silicon substrate LiTaO3 substrate LiTaO3 substrate LiTaO3 substrate SAW filter SAW filter SAW filter Cavity Cavity Cavity Polymer pattern on PICS Polymer pattern on PICS Polymer pattern on PICS PICS substrate PICS substrate PICS substrate Assembly: Assembly: Assembly: Thermo-compression Thermo-compression Thermo-compression Assembly enabling an electrical Assembly enabling an electrical Assembly enabling an electrical contact and sealing contact and sealing contact and sealing PICS substrate LiTaO3 LiTaO3 1mm 1mm SAW filter Polymer seal ring Gold stud-bump 27 Journée EEA Montpellier Philippe Cauvet, Mar 28, 2007
MEMS Acceloremeter stacked die package STMicroelectronics Targeted applications Toys, medicals, phones, anti-theft – 4.3x4.0x0.4mm MEMS die 3.9x4.0x0.4mm cap die 3x2.8x0.2mm logic die QFN 28 I/O, 2 stacked die Die to die and die-leadframe wirebonds 28 Journée EEA Montpellier 26 Philippe Cauvet, Mar 28, 2007
Outline • Definition • Market / Applications • Design and technology • Packaging Technologies • Test Challenges • Conclusion 29 Journée EEA Montpellier Philippe Cauvet, Mar 28, 2007
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