Single-Armed Cluster Tools ISysE, KAIST Yuchul Lim and Tae-Eog Lee - PowerPoint PPT Presentation

Schedulability Analysis and Cyclic Scheduling of Single-Armed Cluster Tools ISysE, KAIST Yuchul Lim and Tae-Eog Lee

Introduction  What is cluster tools?  Wafer processing modules which are widely used in manufacturing systems.  Consist of processing modules, a transporting module, and loadlocks.  How to wafers in a cluster tools are processed  A wafer is unloaded which is pumped to the loadlock from outside.  A wafer visits PMs with specified recipe < PM 2 > < PM 2 > (generally series-parallel wafer flow pattern)  A wafer can be transported only by a robot. (transporting module) < PM 3 > < PM 1 >  A wafer is loaded into the loadlock and vented.  A robot in a tool can be single or dual armed. <Loadlock> <Loadlock> Single − armed Cluster tools < with (1,2,1) wafer flow pattern > 2

Introduction  Here, we focused on the time-constrained single-armed cluster tools  The single-armed robot is equipped in a tool.  PMs in a tool have wafer residency time constraints.  Schedulability analysis of cluster tools  We analyze the schedulability of the backward sequence for cluster tools.  The backward sequence is always feasible in a general cluster tool, and guarantees minimum cycle time.  In a general cluster tool, there always exists feasible schedules of the sequence which has no deadlock by the resources.  However, in consideration of the wafer residency time constraints, feasible sequence in a general cluster tool does not always have feasible schedules.  Schedulability of the sequence in a time-constrained cluster tools is equivalent to the existence of feasible schedules that satisfies all time constraints in the sequence. 3

Introduction  Single-armed cluster tools and Backward sequence  We will use timed event graphs(TEG) which is subclass of timed Petri nets. 𝑉 1 𝑀 1 𝑀 2 𝑀 𝑀𝑀 𝑉 1 𝑀 2 𝑉 𝑀𝑀 𝑉 2 𝑉 𝑀𝑀 𝑉 2 𝑀 𝐽𝐶 𝑀 1 <Petri-net modeling of single-armed cluster tools> <Timed event graph of backward sequence> 4

Research Classification  Scheduling Method  Generation of the sequences  Controlling delay on the backward sequence  How we can know that certain sequence is schedulable or not???  Process time  Deterministic  Bounded time variation  Residency Time Constraints  PM  TM  Loadlock  Controllable TM Task  All TM Task  Limited Task 5

Contents 1) Controlling delays on the backward sequence(deterministic) 1) Controlling delays on the backward sequence(deterministic) A. Existing schedulability analysis of the backward sequence A. Existing schedulability analysis of the backward sequence B. Schedulability analysis of the backward sequence by joint delay control B. Schedulability analysis of the backward sequence by joint delay control A. Properties of the schedulability for the backward sequence A. Properties of the schedulability for the backward sequence B. O(n) algorithm for the schedulability analysis B. O(n) algorithm for the schedulability analysis 2) Controlling delays on the backward sequence(stochastic) 2) Controlling delays on the backward sequence(stochastic) A. Cyclic scheduling with bounded time variation A. Cyclic scheduling with bounded time variation B. Lower bound schedulability analysis B. Lower bound schedulability analysis 3) Workload balancing by controlling WIP(Work in Process) 3) Workload balancing by controlling WIP(Work in Process) 6

Introduction Definition 1-1 : Classification of the circuits - 𝑞 𝑘 𝜗 𝐷 0 𝑗𝑔 𝑞 𝑘 𝜗 𝑄 𝑈𝑁 - 𝑢 𝑘 𝜗 𝐷 0 𝑔𝑝𝑠 𝑏𝑚𝑚 𝑘 - 𝑞 𝑘 𝜗 𝐷 𝑙 𝑗𝑔 𝑞 𝑘 𝜗 𝑄 𝑈𝑁 , 𝑏𝑜𝑒 𝑣 𝑙 → 𝑞 𝑘 → 𝑚 𝑙 𝑔𝑝𝑠 𝑙 > 0 - 𝑞 𝑘 𝜗 𝐷 𝑙 𝑗𝑔 𝑞 𝑘 𝜗 𝑄 𝑄𝑁 , 𝑏𝑜𝑒 𝑚 𝑙 → 𝑞 𝑘 → 𝑣 𝑙 𝑔𝑝𝑠 𝑙 > 0 - 𝑢 𝑘 𝜗 𝐷 𝑙 𝑥ℎ𝑓𝑠𝑓 𝑣 𝑙 → 𝑢 𝑘 → 𝑚 𝑙 𝑔𝑝𝑠 𝑙 > 0 Interpretation of Definition 1-1 : - For TEG of general cluster tools, there exist (n+1) circuits; n for PMs, 1 for the TM. - TM circuit consists of all TM actions. - PM k circuit consists of TM actions from 𝑣 𝑙 to 𝑚 𝑙 , and a processing of 𝑄𝑁 𝑙 . - For the processing of 𝑄𝑁 𝑙 , input transition is 𝑚 𝑙 , and output transition is 𝑣 𝑙 . - To reduce the wafer residency time on 𝐐𝐍 𝐥 , we will give delay on TM actions from 𝒗 𝒍 to 𝒎 𝒍 , which are 𝒒 𝒌 𝒒 𝒌 𝝑 {𝑫 𝒍 ∩ 𝑫 𝟏 } . 7

Controlling delays on the backward sequence(deterministic)  Existing schedulability analysis of the backward sequence 𝑉 1 𝑀 𝑀𝑀 𝑀 2 𝑉 2 𝑉 𝑀𝑀 𝑀 1 𝑠 0 𝑠 𝑠 2 1 <Timed event graph of backward sequence> - All-wait backward operation - controls delay between 𝑚 𝑙−1 and 𝑣 𝑙 for 𝑄𝑁 𝑙  Schedulability : ℎ 𝑄𝑁𝑙 +4𝑥+3𝑤 - 𝜇 𝑄𝑁 𝑙 = ′ = 𝜇 𝑈𝑁 + 𝑛 𝑙 𝜈 0 𝑠 𝑙 - 𝜇 𝑈𝑁 = 2 𝑜 + 1 𝑥 + 𝑤 𝑙≥1 𝜇 ∗ = 𝜈 0 ≥ 𝜈 0 ′ - 𝜇 ∗ = max max 𝜇 𝑄𝑁 𝑙 , 𝜇 𝑈𝑁 𝜇 ∗ = 𝜈 𝑙 = 𝜇 𝑄𝑁 𝑙 + 𝑠 𝑙 𝑙 𝑛 𝑙 ℎ 𝑄𝑁𝑙 +4𝑥+3𝑤+𝜀 𝑄𝑁𝑙 𝑙 = 𝑛 𝑙 · max 0, 𝜇 ∗ − - 𝑠 𝑛 𝑙 8

Controlling delays on the backward sequence(deterministic)  Schedulability analysis of the backward sequence by joint delay control Linear Programming for the backward sequence(deterministic) - Schedulability of backward sequence is equivalent to feasibility of following LP. - Minimized cycle time is equivalent to optimal value of following LP. 𝑁𝑗𝑜𝑗𝑛𝑗𝑨𝑓 𝜇 𝑇𝑣𝑐𝑘𝑓𝑑𝑢 𝑢𝑝 ℎ 𝑄𝑁 𝑙 + 𝑒 𝑄𝑁 𝑙 + 4𝑥 + 3𝑤 + 𝑞 𝑘 𝜗𝐷 𝑙 𝑒 𝑘 = 𝑛 𝑙 𝜇 𝑔𝑝𝑠 𝑙 > 0 𝑥 + 𝑤 + 𝑞 𝑘 ∈𝐷 0 𝑒 𝑘 = 𝜇 2 𝑜 + 1 𝑒 𝑘 ≥ 0 𝑔𝑝𝑠 𝑏𝑚𝑚 𝑘 𝒆 𝑸𝑵 𝒍 ≤ 𝜺 𝑸𝑵 𝒍 𝒈𝒑𝒔 𝒍 > 𝟏 [ℎ 𝑄𝑁 2 , ℎ 𝑄𝑁 2 + 𝜀 2 ] [ℎ 𝑄𝑁 1 , ℎ 𝑄𝑁 1 + 𝜀 1 ] 𝜇 ∶ 𝑑𝑧𝑑𝑚𝑓 𝑢𝑗𝑛𝑓 ℎ 𝑄𝑁 𝑙 ∶ 𝑞𝑠𝑝𝑑𝑓𝑡𝑡𝑗𝑜𝑕 𝑢𝑗𝑛𝑓 𝑝𝑔 𝑄𝑁 𝑙 𝑀 𝑀𝑀 𝑉 1 𝑀 2 𝑉 𝑀𝑀 𝑉 2 𝑀 1 𝜀 𝑄𝑁 𝑙 ∶ 𝑥𝑏𝑔𝑓𝑠 𝑠𝑓𝑡𝑗𝑒𝑓𝑜𝑑𝑧 𝑢𝑗𝑛𝑓 𝑚𝑗𝑛𝑗𝑢 𝑛 𝑙 ∶ 𝑢ℎ𝑓 𝑜𝑣𝑛𝑐𝑓𝑠 𝑝𝑔 𝑞𝑏𝑠𝑏𝑚𝑚𝑓𝑚𝑡 𝑝𝑔 𝑄𝑁 𝑙 𝑤 𝑥 𝑥 𝑤 𝑥 𝑤 𝑥 𝑤 𝑥 𝑤 𝑥 𝑥 ∶ 𝑣𝑜 𝑚𝑝𝑏𝑒𝑗𝑜𝑕 𝑢𝑗𝑛𝑓 𝑝𝑔 𝑏 𝑠𝑝𝑐𝑝𝑢 𝑤 ∶ 𝑛𝑝𝑤𝑗𝑜𝑕 𝑢𝑗𝑛𝑓 𝑝𝑔 𝑏 𝑠𝑝𝑐𝑝𝑢 9 𝑤

Controlling delays on the backward sequence(deterministic)  Schedulability analysis of the backward sequence by joint delay control Theorem 1-1 : - For series-parallel single-armed cluster tools, if the backward sequence is schedulable with cycle time 𝝁 , the backward sequence with cycle time 𝝁 ′ 𝒖𝒊𝒃𝒖 𝒕𝒃𝒖𝒋𝒕𝒈𝒋𝒇𝒕 𝝁 ≥ 𝝁 ′ ≥ 𝝁 ∗ is schedulable. ℎ 𝑄𝑁𝑙 +4𝑥+3𝑤 - 𝜇 ∗ = max(max , 2 𝑜 + 1 𝑥 + 𝑤 ) , which is minimum workload of the tool. 𝑛 𝑙 𝑙>0 Theorem 1-2 : - For series-parallel single-armed cluster tools, if the backward sequence is schedulable with wafer residency time 𝐸 = 𝑒 𝑄𝑁 1 , … , 𝑒 𝑄𝑁 𝑜 , the backward sequence with 𝑬 ′ = ′ 𝒊 𝑸𝑵 𝒍 +𝟓𝒙+𝟒𝒘+𝒆 𝑸𝑵 𝒍 𝒊 𝑸𝑵 𝒍 +𝟓𝒙+𝟒𝒘+𝒆 𝑸𝑵 𝒍 ′ ′ 𝒆 𝑸𝑵 𝟐 , … , 𝒆 𝑸𝑵 𝒐 𝒖𝒊𝒃𝒖 𝒕𝒃𝒖𝒋𝒕𝒈𝒋𝒇𝒕 ≤ ≤ 𝝁 is schedulable. 𝒏 𝒍 𝒏 𝒍 10

Controlling delays on the backward sequence(deterministic)  Schedulability analysis of the backward sequence by joint delay control Schedulability analysis for the backward sequence(deterministic) - Backward sequence is schedulable iff the optimal value of following LP with 𝜇 ∗ = ℎ 𝑄𝑁𝑙 +4𝑥+3𝑤 ℎ 𝑄𝑁𝑙 +4𝑥+3𝑤+𝜀 𝑄𝑁𝑙 and 𝑒 𝑄𝑁 𝑙 = max 0, 𝜇 ∗ − is less than 𝜇 ∗ . max 𝑛 𝑙 𝑛 𝑙 𝑙>0 𝑁𝑗𝑜𝑗𝑛𝑗𝑨𝑓 Σ 𝑞 𝑘 ∈ 𝐷 𝑙 ∩ 𝐷 0 ∀𝑙 𝑒 𝑘 + 2(𝑜 + 1)(𝑥 + 𝑤) 𝑇𝑣𝑐𝑘𝑓𝑑𝑢 𝑢𝑝 ℎ 𝑄𝑁 𝑙 + 𝑒 𝑄𝑁 𝑙 + 4𝑥 + 3𝑤 + 𝑞 𝑘 𝜗𝐷 𝑙 𝑒 𝑘 = 𝑛 𝑙 𝜇 ∗ 𝑔𝑝𝑠 𝑙 > 0 𝑒 𝑘 ≥ 0 𝑔𝑝𝑠 𝑏𝑚𝑚 𝑘 [ℎ 𝑄𝑁 2 , ℎ 𝑄𝑁 2 + 𝜀 2 ] [ℎ 𝑄𝑁 1 , ℎ 𝑄𝑁 1 + 𝜀 1 ] 𝜇 ∶ 𝑑𝑧𝑑𝑚𝑓 𝑢𝑗𝑛𝑓 ℎ 𝑄𝑁 𝑙 ∶ 𝑞𝑠𝑝𝑑𝑓𝑡𝑡𝑗𝑜𝑕 𝑢𝑗𝑛𝑓 𝑝𝑔 𝑄𝑁 𝑙 𝑀 𝑀𝑀 𝑉 1 𝑀 2 𝑉 𝑀𝑀 𝑉 2 𝑀 1 𝜀 𝑄𝑁 𝑙 ∶ 𝑥𝑏𝑔𝑓𝑠 𝑠𝑓𝑡𝑗𝑒𝑓𝑜𝑑𝑧 𝑢𝑗𝑛𝑓 𝑚𝑗𝑛𝑗𝑢 𝑛 𝑙 ∶ 𝑢ℎ𝑓 𝑜𝑣𝑛𝑐𝑓𝑠 𝑝𝑔 𝑞𝑏𝑠𝑏𝑚𝑚𝑓𝑚𝑡 𝑝𝑔 𝑄𝑁 𝑙 𝑤 𝑥 𝑥 𝑤 𝑥 𝑤 𝑥 𝑤 𝑥 𝑤 𝑥 𝑥 ∶ 𝑣𝑜 𝑚𝑝𝑏𝑒𝑗𝑜𝑕 𝑢𝑗𝑛𝑓 𝑝𝑔 𝑏 𝑠𝑝𝑐𝑝𝑢 𝑤 ∶ 𝑛𝑝𝑤𝑗𝑜𝑕 𝑢𝑗𝑛𝑓 𝑝𝑔 𝑏 𝑠𝑝𝑐𝑝𝑢 𝑤 11