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SCRAM Introduction Philipp Koehn 13 September 2019 Philipp Koehn - PowerPoint PPT Presentation

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SCRAM Introduction Philipp Koehn 13 September 2019 Philipp Koehn Computer Systems Fundamentals: SCRAM Introduction 13 September 2019 A Simple Computer 1 Fully work through a computer circuit assembly code Simple but Complete

  1. SCRAM Introduction Philipp Koehn 13 September 2019 Philipp Koehn Computer Systems Fundamentals: SCRAM Introduction 13 September 2019

  2. A Simple Computer 1 • Fully work through a computer – circuit – assembly code • Simple but Complete Random Access Machine (SCRAM) – every instruction is 8 bit – 4 bit for op-code: 9 different operations (of 16 possible) – 4 bit for address: 16 bytes of memory • Background reading on web page: "The SCRAM" Philipp Koehn Computer Systems Fundamentals: SCRAM Introduction 13 September 2019

  3. Operations 2 Operation Code Description HLT 0000 Halt, stop execution LDA 0001 Load value from memory into accumulator LDI 0010 Indirectly load value from memory into accumulator STA 0011 Store value from accumulator into memory STI 0100 Indirectly store value from accumulator into memory ADD 0101 Add value from memory to accumulator SUB 0110 Subtract value from memory from accumulator JMP 0111 Jump to specified address JPZ 1000 Jump to specified address if zero flag is set Philipp Koehn Computer Systems Fundamentals: SCRAM Introduction 13 September 2019

  4. Indirect Load? 3 • LDA x – loads the value from address x • LDI x – looks up the value at address x – treats that value as an address – loads the value at that address • Indirect load = use of pointer variable Philipp Koehn Computer Systems Fundamentals: SCRAM Introduction 13 September 2019

  5. Instruction Encoding 4 Instruction Data 0 0 0 1 0 1 0 1 LDA 5 Load contents from address 5 into memory Philipp Koehn Computer Systems Fundamentals: SCRAM Introduction 13 September 2019

  6. A Simple Program 5 Address Code Meaning op-code data operation data 0 0001 0100 LDA 4 1 0101 0101 ADD 5 2 0011 0100 STA 4 3 0111 0000 JMP 0 4 1111 0000 DAT 0 5 1111 0001 DAT 1 • Note: DAT is not a real instruction • Produces sequence of numbers: 0, 1, 2, 3, 4, ..., 255, 0, .... Philipp Koehn Computer Systems Fundamentals: SCRAM Introduction 13 September 2019

  7. 6 components Philipp Koehn Computer Systems Fundamentals: SCRAM Introduction 13 September 2019

  8. Memory 7 • 4 bits to address memory ⇒ 16 different values ⇒ 16 byte address space • We need to build circuitry to retrieve and store values Philipp Koehn Computer Systems Fundamentals: SCRAM Introduction 13 September 2019

  9. Registers 8 • Accumulator (AC) – can be directly accessed from logic units – used to store the results of computations • Program counter (PC) – memory address of current instruction • Instruction register (IR) – contains current instruction – breaks it down into operation code • Memory registers – memory access register (MAR): address to retrieve value – memory buffer register (MBR): retrieved value Philipp Koehn Computer Systems Fundamentals: SCRAM Introduction 13 September 2019

  10. Arithmetic Logic Unit (ALU) 9 • Can do addition and subtraction • Operands – operand 1: accumulator – operand 2: adress specified in instruction – result: accumulator • Zero flag: result of operation is zero • Carry flag: operation results in overflow / underflow Philipp Koehn Computer Systems Fundamentals: SCRAM Introduction 13 September 2019

  11. Program Counter 10 • 4 bit current memory address of instruction • Typically increased by 1 during each instruction execution • Can also be changed by jump instructions (JMP, JPZ) Philipp Koehn Computer Systems Fundamentals: SCRAM Introduction 13 September 2019

  12. Control Logic Unit 11 • Decodes the op code • Selects instruction logic • Instruction logic: microprogram (sequence of register transfers) • More detail on that in a bit... Philipp Koehn Computer Systems Fundamentals: SCRAM Introduction 13 September 2019

  13. Putting it All Together 12 +---------------------------------+---------------------------------+ | | | | | Memory | | Program Counter (PC) | | | | Memory access register (MAR) | | Instruction Register (IR) | | | | Memory buffer register (MBR) | | | | +---------------------------------+---------------------------------+ | | | | | | | | Accumulator (A) | | Control Logic Unit (CLU) | | | | Arithmetric Logic Unit (ALU) | | | | | | | +---------------------------------+---------------------------------+ Philipp Koehn Computer Systems Fundamentals: SCRAM Introduction 13 September 2019

  14. 13 memory Philipp Koehn Computer Systems Fundamentals: SCRAM Introduction 13 September 2019

  15. 16x8 Bit RAM 14 W A 16x8 RAM DI DO • 16 byte of memory • Inputs – address (A) – data in (DI) – write flag (W) • Output – data out (DO) Philipp Koehn Computer Systems Fundamentals: SCRAM Introduction 13 September 2019

  16. Memory with its Registers 15 W W A MAR 16x8 RAM DO DI W MBR • Memory address register (MAR) • Memory buffer register (MBR) • Each of them has a write flag (there will be a few more of them...) Philipp Koehn Computer Systems Fundamentals: SCRAM Introduction 13 September 2019

  17. 16 instruction fetch Philipp Koehn Computer Systems Fundamentals: SCRAM Introduction 13 September 2019

  18. Program Counter 17 W W A MAR 16x8 RAM W PC DO DI INC W MBR • Program counter contains address of current instruction • This address needs to be passed to MAR • Program counter also needs an easy way to be incremented Philipp Koehn Computer Systems Fundamentals: SCRAM Introduction 13 September 2019

  19. Instruction Register 18 W W A MAR 16x8 RAM W PC DO DI INC W MBR W IR • Content of memory (MBR) is transferred to instruction register Philipp Koehn Computer Systems Fundamentals: SCRAM Introduction 13 September 2019

  20. Instruction Fetch 19 • Program counter (PC) contains address of current instruction • Step 1: copy PC value to memory access register (MAR) • Step 2: retrieve address value into memory buffer register (MBR) • Step 3: copy MBR value into instruction register (IR) • Step 4: increase PC • These copy instructions are triggered by write flags Philipp Koehn Computer Systems Fundamentals: SCRAM Introduction 13 September 2019

  21. MAR ← PC 20 W W A MAR 16x8 RAM W PC DO DI INC W MBR W IR • Copy PC value to memory access register (MAR) Philipp Koehn Computer Systems Fundamentals: SCRAM Introduction 13 September 2019

  22. MBR ← M 21 W W MAR A 16x8 RAM W PC DI DO INC W MBR W IR • Retrieve address value into memory buffer register (MBR) Philipp Koehn Computer Systems Fundamentals: SCRAM Introduction 13 September 2019

  23. IR ← MBR 22 W W MAR A 16x8 RAM W PC DI DO INC W MBR W IR • Copy MBR value into instruction register (IR) Philipp Koehn Computer Systems Fundamentals: SCRAM Introduction 13 September 2019

  24. PC ← PC + 1 23 W W A MAR 16x8 RAM W PC DO DI INC W MBR W IR • Increase PC Philipp Koehn Computer Systems Fundamentals: SCRAM Introduction 13 September 2019

  25. Micro Program 24 • We can write these steps in a register transfer language Time Command MAR ← PC t 0 MBR ← M t 1 IR ← MBR t 2 PC ← PC + 1 t 3 • Execution in time steps t n triggered by the clock Philipp Koehn Computer Systems Fundamentals: SCRAM Introduction 13 September 2019

  26. Parallel Execution 25 • Increase of the program counter is independent from retrieving data from memory ⇒ These steps can be parallized • New micro program Time Command MAR ← PC t 0 MBR ← M, PC ← PC + 1 t 1 IR ← MBR t 2 Philipp Koehn Computer Systems Fundamentals: SCRAM Introduction 13 September 2019

  27. MBR ← M, PC ← PC + 1 26 W W A MAR 16x8 RAM W PC DO DI INC W MBR W IR • Parallel execution of memory retrieve and program counter increase Philipp Koehn Computer Systems Fundamentals: SCRAM Introduction 13 September 2019

  28. 27 control logic unit Philipp Koehn Computer Systems Fundamentals: SCRAM Introduction 13 September 2019

  29. Control Logic Unit 28 W W A MAR 16x8 RAM W PC DO DI INC W MBR W IR C D Decoder Instruction: op-code and data Q Control logic unit Control receives operation code Logic Unit Op-code is decoded into 9 different operations Philipp Koehn Computer Systems Fundamentals: SCRAM Introduction 13 September 2019

  30. Control Logic Unit 29 W W A MAR 16x8 RAM W PC DO DI INC W MBR W IR C D Decoder Q Time step needs to be Control Logic increased Unit or cleared to 0 NOT INC CLEAR after each micro command T Philipp Koehn Computer Systems Fundamentals: SCRAM Introduction 13 September 2019

  31. Control Logic Unit 30 W W A MAR 16x8 RAM W PC DO DI INC W MBR W IR C D Decoder Q Control Time step Logic Unit triggers one command line T NOT in control logic unit INC CLEAR Decoder T Philipp Koehn Computer Systems Fundamentals: SCRAM Introduction 13 September 2019

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