Role of mask on the contact etching for 14nm nodes MEBARKI Mokrane 1,2,3 Maxime Darnon 2 , Cecile Jenny 1 , Nicolas Posseme 3 , Delia Ristoiu 1 ,Germain Servanton 1 , Olivier Joubert 2 1 ST Microelectronics 2 Laboratoire des technologies de la microélectronique (LTM) CNRS 3 CEA LETI PESM Monday, May 12 2014 Grenoble, France
Outline 2 Double patterning for contact etching Double patterning strategy • Mask Opening • Comparison between N 2 /H 2 vs COS/O 2 Silicon oxide etching • Interaction with OPL mask opening process Conclusion PESM 2014- mokrane.mebarki@st.com
Double patterning for contact etching: 3 Increase the number of Reduce the transistors Change of contacts transistors on a chip dimension patterning strategy Double patterning First patterning Si 3 N 4 1. TiN deposition PESM 2014- mokrane.mebarki@st.com
Double patterning for contact etching: 3 Increase the number of Reduce the transistors Change of contacts transistors on a chip dimension patterning strategy Double patterning First patterning Si 3 N 4 1. TiN deposition 2. Trilayer line pattern Cross section post OPL etching PESM 2014- mokrane.mebarki@st.com
Double patterning for contact etching: 3 Increase the number of Reduce the transistors Change of contacts transistors on a chip dimension patterning strategy Double patterning First patterning TiN Hard mask Si 3 N 4 2. Trilayer line 1. TiN deposition 3. Post etching of pattern TiN hard mask Cross section post OPL etching PESM 2014- mokrane.mebarki@st.com
Double patterning for contact etching: 4 Increase the number of Reduce the transistors Change of contacts transistors on a chip dimension patterning strategy Double patterning Second patterning (Cross section) TiN Hard mask TiN Hard mask Si 3 N 4 1. Post etching of 2. Trilayer OPL TiN hard mask mask pattern Cross section post OPL etching PESM 2014- mokrane.mebarki@st.com
Double patterning for contact etching: 4 Increase the number of Reduce the transistors Change of contacts transistors on a chip dimension patterning strategy Double patterning Second patterning (Cross section) TiN Hard mask TiN Hard mask Si 3 N 4 1. Post etching of 2. Trilayer OPL 3. Post OPL TiN hard mask mask pattern mask etching PESM 2014- mokrane.mebarki@st.com
Double patterning for contact etching: 4 Increase the number of Reduce the transistors Change of contacts transistors on a chip dimension patterning strategy Double patterning Second patterning (Cross section) TiN Hard mask Contact Si 3 N 4 TiN Hard mask 1. Post etching of 2. Trilayer OPL 3. Post OPL mask 4. Post Silicon TiN hard mask mask pattern etching oxide etching PESM 2014- mokrane.mebarki@st.com
Double patterning for contact etching: 5 OPL strip Post contact etching Double patterning TEOS opening TiN TiN TiN TEOS Contact opening SEM Top view post contact etching SEM cross section post contact etching PESM 2014- mokrane.mebarki@st.com
Double patterning for contact etching: 6 Increase the number of Reduce the transistors Change of contacts transistors on a chip dimension patterning strategy Double patterning Second patterning (Cross section) TiN Hard mask TiN Hard mask Si 3 N 4 TiN Hard mask Contact 4. Post Silicon oxide 1. Post etching of 2. Trilayer OPL 3. Post OPL TiN hard mask mask pattern etching mask etching PESM 2014- mokrane.mebarki@st.com
Characteristics of OPL etching: 7 OPL etching With N 2 /H 2 OPL etching With COS/O 2 (5%) SiARC Etch rate of OPL according the COS ratio SiARC OPL TiN OPL TiN TEOS TEOS Consumption of SiARC Presence of undercut on sidewalls of OPL mask OPL etching With COS/O 2 (17%) and shorter over etch The increase of COS ratio leads a SiARC better conservation of OPL mask. OPL TiN TEOS TEOS PESM 2014- mokrane.mebarki@st.com
Characteristics of OPL etching: 8 EDX analysis after OPL etching with COS/O 2 (5%)chemistry : SiARC SiARC observation : Si 3 N 4 Ti OPL OPL � Presence of Ti elements TiN TiN TEOS TEOS S EDX analysis for S element EDX analysis for Ti element EDX analysis after OPL etching with N 2 /H 2 chemistry : SiARC OPL � No significant TiN sputtering OPL TiN TiN TEOS TEOS TEM cross section EDX analysis TEOS Interaction between OPL etching and TiN hard mask PESM 2014- mokrane.mebarki@st.com
Double patterning for contact etching: 9 Increase the number of Reduce the transistors Change of contacts transistors on a chip dimension patterning strategy Double patterning Second patterning (Cross section) TiN Hard mask Contact Si 3 N 4 TiN Hard mask 1. Post etching of 2. Trilayer OPL 3. Post OPL mask 4. Post Silicon TiN hard mask mask pattern etching oxide etching PESM 2014- mokrane.mebarki@st.com
Interaction with mask opening process: 10 Etch-stop presence after contact etching OPL etching with COS/O 2 : for the OPL opening with COS/O 2 (5%) Post contact etching TiN TEOS Taper profiles TEOS TiN The contacts are open after contact OPL etching with N 2 /H 2 : etching for the OPL opening with N 2 /H 2 Post contact etching TiN TEOS Correct profiles PESM 2014- mokrane.mebarki@st.com
Interaction with mask opening process: 11 EDX analysis after oxyde etching : TiOF OPL OPL TiN TiN TEOS TEOS Contact Contact EDX after oxide etching with COS/O 2 (5%) for OPL Opening Veil formation of TiO x F y on the holes patterned PESM 2014- mokrane.mebarki@st.com
Origin of veil formation: 12 OPL etching with COS/O 2 (5%) OPL etching with N 2 /H 2 SiARC SiARC Ti OPL OPL No significant TiN TiN sputtering � Ti residue sputtering TiN TiN TEOS TEOS EDX analysis EDX analysis Hypothesis : Ti sputtering during OPL Over Etch induces veil After contact etching for OPL etching with COS/O 2 (5%) formation during SiO 2 etching Decrease OE time Lower OE � Lower TiN sputtering No TiOF veil PESM 2014- mokrane.mebarki@st.com
Conclusion: OPL etch N 2 /H 2 COS/O 2 Straight OPL mask profile Taper OPL mask profile � Increase ratio of COS/O 2 Low TiN sputter TiN sputter Oxyde etch Veil formation Etch stop Correct Etching � At long OE Contacts open � At short OE PESM 2014- mokrane.mebarki@st.com
PESM Monday , May 12 2014 Grenoble, France Thank you for your attention ! PESM 2014- mokrane.mebarki@st.com
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