RFIC Design for Wireless Communications RFIC Design for Wireless Communications VLSI Design & Test Seminar, April 19, 2006 Foster Dai 1. An An MIMO Multimode WLAN RFIC 1. 2. A ∆Σ ∆Σ Direct Digital Synthesizer IC Direct Digital Synthesizer IC 2. A ∆Σ ∆Σ Foster Dai, April, 2006 1
An MIMO Multimode WLAN RFIC 1. An Overview of MIMO Technology An Overview of MIMO Technology 1. 2. MIMO Transceiver Design MIMO Transceiver Design 2. 3. Transceiver Building Block Circuits Transceiver Building Block Circuits 3. 4. Measured Results Measured Results 4. Dave G. Rahn, Mark S. Cavin, Foster F. Dai, Neric Fong, Richard Griffith, 1 . Jose Macedo, David Moore, John W. M. Rogers, and Mike Toner, “A Fully Integrated Multi-Band MIMO WLAN Transceiver RFIC,” IEEE Journal on Solid State Circuits, Vol. 40, No. 8, pp. 1629-1641, August, 2005. IEEE Symposium on VLSI Circuits , pp. 290 – 293, Kyoto, Japan, June, 2005. Foster Dai, April, 2006 2
Advantages of MIMO Technology • MIMO can extend range and higher data rates 250 • Graph shows that for a 4X4 1x1 MIMO system 16.5dB less S/N 1x2 – SD 200 Average Data Rate (Mbps) 4x4 CBF ratio required for 54MBit/sec 4x4 VCBF compared to standard 150 technology • As well vector CBF is shown 100 16.5dB which uses four orthogonal data streams to increase data 50 rate 4X. 0 • VCBF not implemented here -10 -5 0 5 10 15 20 25 30 35 Average SNR (dB)/Antenna (not backwards compatible), but shows future of this technology. Foster Dai, April, 2006 3
MIMO Transceiver Design Beam Forming Maximum ratio Two Radios in the TX to get Combining at On the same antenna gain through receive of Slave Chip chip signal shaping Slave Chip signals in four paths at the RX Link LO Porting Trace LO Porting Trace Note: Both beam forming and maximum ratio Master Chip combining Master Chip controlled by DSP Transmitting Radio Receiving Radio Foster Dai, April, 2006 4
MIMO Transceiver Design Issues MIMO transceiver RFIC design is a challenge due to the following issues: 1. Multiple radios on same die cause interference, especially PAs cause VCO injection-locking. Careful floor planning and proper isolation in layout are critical. VCOs operate at different frequencies from the PAs. 2. All LOs must be synchronized. MIMO calibration requires loop back measurement to match phase and amplitude of all paths. 3. Tx-Tx isolation must be high to maximize the gain from CBF. 30dB or higher desired. 4. Rx-Rx isolation must be maximized in order to maximize the gain from MCR. 40dB desired. Foster Dai, April, 2006 5
MIMO Transceiver Design Block Diagram PA RFOUT1 Legend: 5GHz Matching Network • Uses walking IF IFLOQ RFMIX architecture for only one VGA PA RFOUT1 IFMIX PPA Path1 2.5GHz synthesizer PPA IFLOI RFLO LNA • Includes 2 a/b/g paths RFIN1 BBI1 Switch 2.5GHz BBLPF IFMIX RFIN1 on each chip. BBQ1 VGA 5GHz Switch LNA RFMIX ∆Σ ∆Σ IFLOQ • Either master or slave XTAL XTAL SYN SYN IFLOI IFLOI Serial to Parallel ÷ 4 ÷ 4 RFLO RFLO Interface PLL mode. VCO VCO RCLPF RCLPF IFLOQ IFLOQ IFLOQ RFMIX LNA • BB filters switched so Switch RFIN2 VGA BBQ2 5GHz IFMIX BBLPF RFIN2 same Si used in Tx and Switch BBI2 2.5GHz LNA RFLO IFLOI Rx. PPA RFOUT2 IFMIX PPA Path2 2.5GHz PA VGA RFMIX IFLOQ RFOUT2 5GHz Foster Dai, April, 2006 PA 6
Synthesizer Design From master or to slave chip LO + Reset Signal off chip VCOs Additional Radio LPF Bi-Directional LO Paths (not shown) Porting Circuit n : IF mixers : RF mixer F Ref F RF Baseband Charge ÷ R PFD Pump I-Q output 1 Reference source RF mixer Multi-modulus Baseband Divider I-Q input 90 ° Course tune frequency Multiple Input ÷ 4 word C F IF + Multiple Output 0 ° Transceiver Fine tune frequency ∆Σ accumulator size F Reset word K + n th order ∆Σ Foster Dai, April, 2006 7
Chip Layout • Designed in a TX1a TX2a 50GHz SiGe BiCMOS MIMO Transceiver TX2b/g technology TX1b/g Porting BB1 BB2 LO • Chip measures IF1 IF2 5.4mmX5.4mm RX2b/g RX1b/g Synthesizer VCO • Placed in a 72pin PFD/CP MMD leadless plastic chip RX1a RX2a carrier (LPCC) ∆Σ ∆Σ SPI package . Foster Dai, April, 2006 8
EVM Measurements A: Ch1 OFDM Meas Range: -15dBm 1.5 Shows typical EVM I-Q measurement which complies with IEEE 300 m /div 802.11a standard. -1.5 -2.715 2.7152 RBW: 312.5kHz TimeLen: 60 Sym B: Ch1 Spectrum Range: -15dBm -10 dBm 10 dB /div -110 Foster Dai, April, 2006 dBm 9 Center: 5.18GHz Span: 36MHz RBW: 11.9344kHz TimeLen: 320.0304uSec
Synthesizer Phase Noise Measurements -60 -70 -80 dBc/Hz) -90 -100 Phase Noise ( -110 -120 -130 -140 -150 -160 0.1 10000 1.0 10 100 1000 Frequency Offset (kHz) • Shows good agreement with measured results. Foster Dai, April, 2006 10
Chip Measurements S UMMARY OF T RANSCEIVER P ERFORMANCE S UMMARY OF T RANSCEIVER P ERFORMANCE Parameter Performance Parameter Performance Band 802.11b/g 802.11a Band 802.11b/g 802.11a 0.5 µ m SiGe BiCMOS Technology Rx Path to Path >50dB > 40dB Isolation (measured at Voltage Supply 2.75V 2.75V the BB filter output) TX Chain Current 240/ 255/ Max DC offset without Supply (1path/2paths) 400mA 430mA 90mV 90mV correction (measured RX Chain Current 195/ 195/ at the output of the BB Supply 320mA 320mA filter) (1path/2paths) 0.35~0.43 ° 0.63~0.86 ° Synthesizer Synthesizer Current 36mA 36mA Integrated Noise rms rms supply 100Hz to 10MHz TX output power 11dBm 13.5dBm VCO Phase Noise -120dBc/Hz -120dBc/Hz EVM at TX output 4% (g only) 4% @ 1MHz @ 1MHz power In Band Phase Noise -98dBc/Hz -98dBc/Hz TX Path to Path > 40dB > 40dB @ 10kHz @ 10kHz Isolation (measured at Synthesizer 40MHz the PA outputs) Reference Frequency RX NF @ Max Gain 4.1dB 7.5dB Synthesizer Step Size 468.75kHz 781.25kHz RX chain Max Gain 77 dB 72 dB RX chain Min Gain 5.5dB 25dB Synthesizer Spurious <-50 dBc Rx IIP3 @ Min Gain +8.8 dBm -12.8 dBm RX I/Q Amplitude 0.3 dB 0.3 dB Imbalance 2.0 ° 2.0 ° RX I/Q Quadrature Error Foster Dai, April, 2006 11
A Multi-Band Σ∆ Σ∆ Fractional-N Frequency Synthesizer John W.M. Rogers, Foster F. Dai, Mark S. Cavin, and Dave G. Rahn, “A Fully Integrated Multi-Band SD Fractional-N Frequency Synthesizer for a MIMO WLAN Transceiver RFIC,” IEEE Journal on Solid State Circuits, Vol. 40, No. 3, pp. 678-689, March, 2005. Foster Dai, April, 2006 12
Demo of Range Improvement Using the MIMO Transceiver RFIC 1x1 1x2sel 4CBFx2sel 4x2 CBF RECEPTION 12 OFFICE OFFICE OFFICE OFFICE OFFICE OFFICE OFFICE CONFER ENCE 1 2 3 5 10 11 3 2 OFFICE OFFICE OFFICE OFFICE 7 9 8 2 OFFICE 22 WORKR OOM OFFICE 21 17 AP 25 COPY R M. 23 PANTRY TELECOMM. WORK R OOM OFFICE MECHAN ICAL OFFICE CONFER ENCE ROOM 15 13 20 18 16 14 OFFICE 19 2 CONFER ENCE ROOM 26 2 24 OFFICE OFFICE OFFICE OFFICE OFFICE OFFICE OFFICE OFFICE OFFICE OFFICE OFFICE 27 28 29 30 31 32 33 34 35 36 37 OFFICE OFFICE 38 39 Scale: 10feet Shows improved range of MIMO radios in an office building at 2.4GHz. 4X4 link range too large to show. Foster Dai, April, 2006 13
Conclusions • Implemented an IEEE 802.11a/b/g transceiver RFIC for 2.4GHz and 5.2GHz and Japan 4.9GHz multi-band MIMO WLAN applications. • Transceiver RFIC includes two complete radio paths fully integrated on the same chip. • Using walking IF architecture, uses a single Σ∆ fractional-N synthesizer for LO generation. • Using two RFICs, 4X4 MIMO radio link has been tested under a typical indoor WLAN environment. • The measured 4X4 MIMO radio achieves 15dB of link margin improvement over a conventional SISO radio. Foster Dai, April, 2006 14
A CMOS Direct Digital Frequency Synthesizer with Single- Stage SD Interpolator and Current-Steering DAC • DDS spurs and quantization noise due to phase truncation. • Frequency domain and phase domain Σ∆ Σ∆ noise shaping schemes. • 12-bit current-steering DAC with Q 2 random walk switching scheme. . Foster F. Dai, Weining Ni, Yin Shi and Richard C. Jaeger, “A Direct Digital 1 Frequency Synthesizer with Single-Stage ∆Σ Interpolator and Current-Steering DAC,” IEEE Journal on Solid State Circuits , Vol. 41, No. 4, pp.839-850, April 2006. IEEE Symposium on VLSI Circuits , pp. 56–59, Kyoto, Japan, June, 2005. Foster Dai, April, 2006 15
Conventional ROM-Based DDS Fine step size requires a large accumulator and a large ROM. To reduce ROM size, the phase word is truncated, causing spurs at DDS output. Sampled sin D amplitude bits waveform Numerically controlled oscillator (NCO) 2 P phase addresses Phase truncation Frequency D-bits P Deglitch SIN Phase control word DAC LPF look up accumulator (FCW) D B ~ table f S DAC ~ N N ~ M o + L S N-P B N Phase to Z -1 Truncated amplitude phase conversion Filtered sin waveform Phase FCW = f f o clk Digitized sin N 2 amplitude Foster Dai, April, 2006 16
DDS Pros and Cons • Advantages Fine frequency tuning resolution Fast frequency switching Quadrature outputs with accurate I/Q matching Direct modulations (PSK, FSK, MSK, PM, and FM) Compatible with digital CMOS processing • Disadvantages Low output frequency Quantization noise and spurious tones Foster Dai, April, 2006 17
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