Research of Germanium on Insulator Haiyan Jin, visiting scholar - PowerPoint PPT Presentation

1 Research of Germanium on Insulator Haiyan Jin, visiting scholar Collaborators: Eric Liu and Prof.Nathan Cheung EECS , UC Berkeley The work is supported by the UC Discovery FLCC and IMPACT programs Seminor S eminar Feb. 28 th , 2008 GOI

2 Institute of Microelectronics Peking University, Beijing, China Wang Yangyuan Professor and Director of ULSI SOC MEMS Institute of Microelectronics Professors : 49 Undergraduate students : 60~80/year Graduate students : 40~55/year Seminor S eminar Feb. 28 th , 2008 GOI

3 National Key Micrometer/Nanometer Processing Lab • Over 10-million USD process and analyzing 2 equipment in a 900m clean room. • CMOS, Bipolar, especially MEMS baseline process. Seminor S eminar Feb. 28 th , 2008 GOI

4 OUTLINE Part I State of the art on GeOI • An introduction to GeOI • Main approaches for GeOI fabrication Part II Our research about GeOI • Bulk and Epi Ge wafer are transferred on substrate • A new method was presented to extract mobility • Mobility and interface trap density are improved Seminor S eminar Feb. 28 th , 2008 GOI

5 Part I State of the art on GeOI • An introduction to GeOI What is GeOI ? GeOI = “Ge”+ “OI” Ge Si SiO2 SiO2 Si substrate Si substrate SOI GeOI Seminor S eminar Feb. 28 th , 2008 GOI

6 Why GeOI ? Advantages of “ “Ge Ge” ” Advantages of • Significantly higher bulk electron and hole mobilities mobilities • Significantly higher bulk electron and hole • Higher thermal injection velocity • Higher thermal injection velocity • Lower Schottky Schottky barrier due to smaller barrier due to smaller Ge Ge band band- -gap gap • Lower • Allowing a smaller V DD • Allowing a smaller V DD Advantages of “ “on on- -Insulator Insulator” ” Advantages of • Partially overcoming the high leakage current • Partially overcoming the high leakage current • Potential substrate for FinFET FinFET structures structures • Potential substrate for Seminor S eminar Feb. 28 th , 2008 GOI

7 • Texas Instruments' first IC made by Jack Kilby in 1958 • The first transistor was invented in 1947 by William Shockley, John Bardeen and Walter Brattain. The first transistor and IC are all made of Germanium Seminor S eminar Feb. 28 th , 2008 GOI

8 The Myth: Si is the newer technology The Myth: Si is the newer technology Identified by Lavoisier in 1787 In 1886, Coca Cola w as invented In 1886, Coca Cola w as invented B C N Al Si P Ga Ge As It’s the real thing. Germanium. It’s the real thing. Germanium. In Sn Sb Identified in 1886 Seminor S eminar Feb. 28 th , 2008 GOI

9 Part I State of the art on GeOI • An introduction to GeOI • Main approaches for GeOI fabrication Ge condensation method Rapid Melt Growth Mechanical and Thermal Ion-Cut Seminor S eminar Feb. 28 th , 2008 GOI

10 Ge condensation method (This method is first presented by S.Nakaharai, MIRAI-ASET, Japan) Planar defects TEM • Ge condensation technique: (a) Commercial SOI wafer, (b) SiGe layer is grown epitaxially on an SOI wafer, (c) Oxidation of SGOI, (d) Complete Ge condensation and (e) GeOI wafer after removing surface oxide. Seminor S eminar Feb. 28 th , 2008 GOI

11 Rapid Melt Growth (RMG) LTO (a) Seed windows are etched (d) Ge stripes is covered by LTO (b) Ge is deposited by CVD (c) Ge film is patterned into stripes TEM image of GeOI obtained by RMG Y.Liu et al., Stanford University Seminor S eminar Feb. 28 th , 2008 GOI

12 Mechanical and Thermal Ion-Cut (1) H + R p Edge initiated Ge wafer cleavage O 2 plasma (Mechanical cut) Si 3 N 4 or SiO 2 Si wafer (a) H+ implantation to Ge (b) Oxygen plasma (c) Ramp anneal at 200~250 ° C (dose:6x10 16 /cm 2 ); activation for 15sec i) LPCVD Si 3 N 4 on Si (2) ii)Thermal SiO 2 on Si A 200mm GeOI formed by thermal-cut method (Soitec, France) Anneal at T>270 ° C (Thermal cut) Seminor S eminar Feb. 28 th , 2008 GOI

13 GeOI device First Deep Sub-Micron GeOI PMOSFET P-Channel Germanium FinFET A.Pouydebasque, et al. Based on RMG (CEA-LETI MINATEC, FRANCE) Jia Feng, et al.(Stanford University), EDL, 2007 Seminor S eminar Feb. 28 th , 2008 GOI

14 Advantages of ion-cut method • Wafer-scale transfer for all wafer sizes • Layout Pattern independent • High quality GeOI decided by bulk Ge or Epi-Ge • An extension of mature SOI technology Seminor S eminar Feb. 28 th , 2008 GOI

15 Part II Our research about GeOI • Bulk and Epi Ge wafers were transferred • A new method was presented to extract mobility • Mobility and interface trap density are improved Seminor S eminar Feb. 28 th , 2008 GOI

16 Large-area GeOI formed by layer transfer processing Transferred Germanium 400nm Ge 850nm Ox 1 cm Si substrate 850nm Ox/Si Fabrication processes: (1) HF/DIW surface cleaning (pre-bonding cleaning); (2) N 2 plasma activation; (3) Direct bonding; (4) Post-bonding annealing at 220 ℃ ; (5)Mechanical-cut or thermal-cut at T>270 ° C ; Seminor S eminar Feb. 28 th , 2008 GOI

17 Pillow defect The pillow defects of GeOI annealt at various temperature. No Ge wafer surface cleaning is performed before wafer bonding. The origin of pillow defects is usually attributed to contamination on the Germanium wafer surface such as hydrocarbons. Seminor S eminar Feb. 28 th , 2008 GOI

18 Layer Transfer Process Improvement (A) (A) (A) (B) (B) (B) 20 µ m 20 µ m 20 µ m 20 µ m (A)GeOI sample after 540 ° C B)GeOI sample after 540 ° C anneal anneal for 90 min without pre- for 90 min with pre-bonding cleaning bonding cleaning Seminor S eminar Feb. 28 th , 2008 GOI

19 Plasma surface activation Bonding energy of Ge with (I) SiO 2 /Si, O 2 plasma surface activation; (II) Si 3 N 4 /Si, O 2 plasma surface activation; (III)SiO 2 /Si, N 2 plasma surface activation. Seminor S eminar Feb. 28 th , 2008 GOI

20 GeOI surface smoothing with CMP • GeOI surface can be smoothed down to RMS =0.3nm by CMP (CMP slurry: 0.2µm SiO2 particle mixed with KOH) • GeOI substrates are ready for device fabrication Seminor S eminar Feb. 28 th , 2008 GOI

21 The GeOI surface smoothing by CMP 0.0 25.0 50.0 75.0100.0 RMS:11.8 nm; Ra:9.5 nm Z-range: 87.8 nm Z[nm] 200nm 0.0 0.20 0.40 0.60 0.80 1.0 (a) as-cut GeOI X[µm] 0.0 25.0 50.0 75.0100.0 RMS: 0.3 nm; Ra: 0.23 nm Z-range: 3 nm Z[nm] 200nm 0.0 0.20 0.40 0.60 0.80 1.0 (b) after CMP and HF dip X[µm] Seminor S eminar Feb. 28 th , 2008 GOI

22 300mm Ge wafers (UMICORE) Seminor S eminar Feb. 28 th , 2008 GOI

23 Surface steps of Epi-Ge wafer AFM image of a Epi-Ge surface Seminor S eminar Feb. 28 th , 2008 GOI

24 Large area Epi-Ge is transferred Si substrate Epi Ge Si substrate Epi Ge donor donor GeOI GeOI 5cm 5cm 3 days furnace annealing 7 days furnace annealing Temperature increases slowly from 120 ℃ to 300 ℃ Seminor S eminar Feb. 28 th , 2008 GOI

25 Part II Our research about GeOI • Bulk and Epi Ge wafer are transferred on substrate • A new method was presented to extract mobility • Mobility and interface trap density are improved Seminor S eminar Feb. 28 th , 2008 GOI

26 Pseudo MOSFET Measurement (4-probe configuration) • Rapid electrical V 2,3 evaluation of I 1,4 A semiconductor-on- V insulator substrate 1 2 3 4 Ge _ • Extracting BOX V G interface carrier + P + -Si substrate mobility of GeOI Seminor S eminar Feb. 28 th , 2008 GOI

27 The pseudo-MOSFET experimental data Experimental data Theoretical data 0.00056 −1 ) G=I 1,4 /V 2,3 ( Ω (I) (II) Inversion Depletion (III) 0.00052 Accumulation 0.00048 V FB =-10.2V V T =6.8V -30 -15 0 15 30 V G (V) G vs VG plot, which shows the accumulation, depletion and inversion regions. In depletion mode, the bulk Ge mobility is extracted by fitting theoretical data with experimental data, which is 143.8cm 2 /V-sec. Seminor S eminar Feb. 28 th , 2008 GOI

28 In inversion mode, Channel conductance G ch is given by: G ch = f g µ n0 C ox (V G -V T ) /[1+ θ (V G -V T )] Seminor S eminar Feb. 28 th , 2008 GOI

29 Differentiating G ch , we obtain: µ f C dG = = g n 0 ox ' ch G [ ] + θ − ch 2 dV 1 ( ) V V G G T ( ) ( ) G = µ − 0 . 5 ch f C V V g n 0 ox G T 0 . 5 ' G ch Seminor S eminar Feb. 28 th , 2008 GOI

30 Experimental data 0.04 0.5 ) 0.5 (S 0.5 Slope=(f g µ n0 C ox ) G ch /G' ch 0.02 Inversion mode V T =6.8V 2 /V-sec µ n0 =87.3cm 0.00 10 20 30 V G (V) The extraction of the threshold voltage V T ; The low field electron mobility at interface was extracted from the slope of the fit lines, which is 87.3cm 2 /V-sec. Seminor S eminar Feb. 28 th , 2008 GOI

31 In accumulation mode: µ f C dG = = g p 0 ox ' ch G [ ] + θ − ch 2 dV 1 ' ( V V ) G G FB ( ) ( ) G = µ − 0 . 5 ch f C V V g p 0 ox G FB 0 . 5 ' G ch Seminor S eminar Feb. 28 th , 2008 GOI