Reliability and Lifetime of Electronics in the cold : past, present and future Veljko Radeka radeka@bnl.gov DUNE CE Workshop 07/16 ‐ 18/2018
Outline 1. CE before cold CMOS: JFETs, discrete and hybrid circuits, from the first JFET (1963) until NA48 ‐ 62 and ATLAS: “Will thermal contraction/expansion cause damage?” 2. MicroBooNE: CMOS FE ASIC, 3 years of stable operation in Lar: “ Has anything changed?” 3. “Reliability” vs “Lifetime”: Random Failures vs Aging 4. CMOS hot electron effects (HCE): How to avoid them? 5. Accelerated stress testing of CMOS and HV capacitors: 6. Ingredients of “reliability” V. Radeka 2
Cryogenic front-end based on JFETs – Helios-NA34 Liquid Argon calorimeter (1985-9) ‐‐ Ceramic hybrid with co ‐ fired traces and surface mount components ‐‐ 576 preamplifiers – Operation: 4 years , multiple cool ‐ downs – Failure: 1 , =<0.2% caused by a mechanical contact It all started with: Single cold JFET with Ge detectors (1965 ‐ 8) V. Radeka 3
Liquid Krypton calorimeter in NA48-NA62 – JFET preamplifiers in LKr : 13,212 channels; surface mounted components – Operated at 5 kV; HV caps had to be realized in PCBs 15 tons of LKr – Failures • ~50 because of an HV accident in 1998 • ~25 cold electronics failures after 1998, < 0.2% – Always kept at LKr temperature since 1998 – Operation: • 20 years so far • Expected to be in operation for >20 years
Reliability of Cold Electronics wrt thermal contraction ‐ expansion PCB and Cold Electronics in ATLAS: EMB Mid/Back MB+SB Assembly • ATLAS LAr Calorimeter – 182,468 readout channels • EM Barrel Mother Board and Summing Board – EMB has ~110,000 detector channels read out by 896 x128-ch FEBs – 960 Mother Boards (MB) – 7,168 Summing Boards (SB) – 20,480 resistor network chips, 0.1% – ~110,000 protection diodes on MBs/SBs • EM Barrel Calorimeter has been cold since 2004 Operation: 14 years so far – – MB/SB will remain in operation without upgrade for super LHC • ‘Inoperative’ channels <0.5%, as of 05/10/2011 • ‘Dead’ channels in the cryostat EMB Wheel C ~0.02% since 2008
PCB and Cold Electronics in ATLAS HEC Preamplifier ASIC based on GaAs • – HEC has ~5,600 detector channels read out by 48x128 ‐ ch FEBs – 320 PSBs installed on HEC wheels, 5 different types – Total ~35,000 cold preamplifier channels, each preamplifier ASIC HEC Type C PSB has 8 channels • HEC Calorimeter has been cooled down since 2005 – Operation: 14 years so far – HEC cold electronics will remain in operation; no upgrade required • Dead channels ~0.37% HEC Rear Wheel V. Radeka 6
PC board and hybrid circuits (Si JFETs and GaAs ICs) • After a few initial failures at installation and commissioning, no failures (so far for 10 to 20 years ). • In the examples given, fewer dead channels within the cryostats than in the warm electronics outside. • “So, the pc board technology in LAr works, but we are concerned about CMOS ….” V. Radeka 7
MicroBooNE long term stability of average MIP response, incl. argon purity variations <0.2 % gain variation MicroBooNE publication
MicroBooNE Gain Stability Analysis by: Brian Kirby V. Radeka 9
MB FE ASIC Transistor Level Design 10 V. Radeka
Hot Carrier Effect (HCE) • Some hot electrons exceed the energy required to create an electron ‐ hole pair, , resulting in impact ionization . Electrons proceed to 1.3 eV i the drain. The holes drift to the substrate. The substrate current is expressed as q E I C I e i m sub 1 ds • A very small fraction of hot electrons exceeds the energy required to create an interface state at the Si ‐ SiO 2 interface, , for 3.7 eV it electrons (~4.6 eV for holes). q = electron charge λ = electron mean free path • Physical model of the generation of interface states can be described as E V V E m = electric field hot electrons that have enough energy to surmount Si ‐ SiO 2 barrier m ds dsat I ds = drain ‐ source current (3 . 1 eV) and break the silicon ‐ hydrogen bond (0 . 3 eV ) generating a W= channel width trivalent silicon atom (interface state) and a hydrogen atom like C 1 , C 2 ‐ constants If the silicon recombines with the hydrogen, no interface state will appear. If the hydrogen atom diffuses away from the interface, interface state will be generated. The total barrier for hot electrons to inject can be calculated as φ it = 3 . 1 eV + 0 . 3 eV = 3 . 4 eV , close to the experimental result (~ 3 . 7 eV ‐ 4 . 1 eV ). 11
COTS: No access to transistor design, but a known process, TSMC 350nm ADC 7274 Life � me Projec � on → V ds =2.5 V well below V node =3.6 V I VCC drops 1% as degradation criteria 3.6V, 150 years Reduced V DS results in making HCE negligible and a very long extrapolated life time. (005) 5.25V, 800 hours is estimated
Hot electrons: Why is the dependence of Lifetime Hot electrons: Why is the dependence of Lifetime on V ds so strong? on V ds so strong? The lifetime is given by, 1 1 C e e it he it he 2 I W I W ds ds Electrons in the MOS channel reach energies well above thermal both at 300K and at 77K . However the mean electron energy, , at the electric field q E 100 meV he m 1.06 in the range E m ≥ 100kV/cm. At 77K it is slightly higher, he 77 K he 300 K 3.7 eV Only a tiny fraction of “hot” electrons reaches the much higher energy it required to create an interface state . This makes the exponent in the relation for the lifetime very large, it it 40 4 q E he m Since , the ratio of lifetimes for two slightly different values of V ds is E V m ds given by, V V 1 it ds 2 ds 2 1 ln 1 for V 1.06 10 V ds 1 2 2 he ds 1
Failure Rate/MTBF(MTTF) and Wear(Aging) • MTBF (Mean Time Between Failures) and Failure Rate λ =1/ MTBF approach to Reliability, assumes a random process, where the failure rate is constant and the distribution of time intervals between failures is given by Poisson statistics. It can be controlled by the design, choice of components, and various quality control tools. • Reliability is defined as the probability that a component (transistor, circuit, subsystem, or entire system) will operate, as specified, over a given time without failure. In terms of Failure Rate, or MTBF, it is given by, t t MTBF R e e 0.999.. MTBF • Mission/Service Life is useful life as limited by any mechanism, random failure, or wear/aging, uniform and understood for a given class of components. • Wear/aging is given by the physical/chemical processes, with all devices of the same type subject to the same process . It can be controlled only by the design and the operating conditions.
Sense Wire Bias Circuit: “What about me?!” • FE ASIC input impedance ~50 (only input stage is shown). • L is a component of the ESD protection circuit. • 22nF taken into account in accurate C c calculations • C C minimum value given by charge calibration accuracy and capacitor tolerance: ∆� � ≅ � � � ∆� � � � � � � � with C W ~200 pF, and a 10% precision in ∆ C C /C C , to reach for ∆ Qi/Qi=0.5% requires • C C >4 nF. • E.g., Choose 4.7 nF @ ~10% tolerance , or 2.2 nF @ 5% tolerance • C C voltage rating: WVDC>2 x operating voltage • C W /C C ratio determines the fraction of charge Q i is NOT being transferred to the amplifier therefore impacts signal to noise ratio. For example, if C C =2.2nF, ~8% of signal charge is not measured by the amplifier.
Besides CMOS, capacitors deserve attention: • The highest risk for the sense wire capacitor C c is it’s cost (~$1.30), comparable to the FE ASIC cost/channel. • The type of capacitor used so far, well proven, e.g., LAr HEC in ATLAS: Kemet C2225X392JGGACTU, CAP CER 3900PF 2KV C0G/NP0 2225, +/ ‐ 5% tolerance. • Finding a lower cost capacitor is a risky enterprise, it may result in a really “ cheap ” capacitor …. • Capacitor life time and accelerated stress testing is a separate field. It requires digging into chemical kinetics, Eyring equation and similar …. V. Radeka 16
Ingredients of “reliability” in LAr • Start with: • ASIC design below the HCE domain (V ds <V node ) • PC board assemblies designed and fabricated to survive repeated immersions in LN2. • Capacitors operating voltage V op <WVDC/2 • Connectors and cables, a testing challenge … • ….. • Formal QA process for everything … V. Radeka 17
Backup Slides V. Radeka 18
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