Ral Torrego Ikerlan-IK4 rtorrego@ikerlan.es INDEX Introduction - PowerPoint PPT Presentation

OQPSK COGNITIVE MODULATOR FULLY FPGA-IMPLEMENTED VIA DYNAMIC PARTIAL RECONFIGURATION AND RAPID PROTOTYPING TOOLS Raúl Torrego Ikerlan-IK4 rtorrego@ikerlan.es

INDEX • Introduction  Software Defined Radios / Cognitive Radios  Rapid prototyping tools and FPGA Partial Reconfiguration • System Implementation  OQPSK modulator  Power Spectral Density estimator  Partial Reconfiguration and system architecture  Partial reconfiguration and rapid prototyping tools  Work algorithm  Test framework • Measurements • Conclusions and future work Index • Questions OQPSK COGNITIVE MODULATOR FULLY FPGA- 2 IMPLEMENTED VIA DYNAMIC PARTIAL RECONFIGURATION AND RAPID PROTOTYPING TOOLS

INTRODUCTION • Requirements to be met by communication systems:  High data rate, heterogeneous communication standard compatibility, reliable communications, high battery life, small size, low price... • Technological answer: Introduction (1 of 3)  Software Defined Radios (Ability to change)  Cognitive Radios (Ability to sense)  Intelligent Radios (Ability to learn) OQPSK COGNITIVE MODULATOR FULLY FPGA- 3 IMPLEMENTED VIA DYNAMIC PARTIAL RECONFIGURATION AND RAPID PROTOTYPING TOOLS

INTRODUCTION • SDR design environment: · Graphical programming, no code writing. Rapid prototyping · Early functional tools simulations ·Easy debugging - Communication system where a single piece of hardware has Fit perfectly different functionalities in different times Introduction (2 of 3) · Design flexibility FPGA partial · Hardware reuse. reconfiguration · Power save (PR) OQPSK COGNITIVE MODULATOR FULLY FPGA- 4 IMPLEMENTED VIA DYNAMIC PARTIAL RECONFIGURATION AND RAPID PROTOTYPING TOOLS

INTRODUCTION • Proposed application  Cognitive Radios in wireless industrial communications • Proposed implementation  OQPSK modulator (WirelessHART/IEEE802.11.4) Introduction (3 of 3)  Channel sensing  Transmission in free channel OQPSK COGNITIVE MODULATOR FULLY FPGA- 5 IMPLEMENTED VIA DYNAMIC PARTIAL RECONFIGURATION AND RAPID PROTOTYPING TOOLS

IMPLEMENTATION • Two signal processing tasks  OQPSK modulator  Power Spectral Density estimator • Chosen rapid prototyping tool Implementation (1 of 7)  Xilinx’s System Generator OQPSK COGNITIVE MODULATOR FULLY FPGA- 6 IMPLEMENTED VIA DYNAMIC PARTIAL RECONFIGURATION AND RAPID PROTOTYPING TOOLS

IMPLEMENTATION • OQPSK modulator implementation Modulator Oscillator Implementation (2 of 7) Differential Data acquisition encoder • Basic characteristics: - 2 Mbps - FI: 5-10 MHz (PR implemented) - Output filter: 64 tap, 0.25 roll-off OQPSK COGNITIVE MODULATOR FULLY FPGA- 7 IMPLEMENTED VIA DYNAMIC PARTIAL RECONFIGURATION AND RAPID PROTOTYPING TOOLS

IMPLEMENTATION • PSD estimator implementation Power detector FFT Implementation (3 of 7) • Basic characteristics: - FFT: 64 tap - Fs: 61.44 MHz - Resolution: 1 MHz OQPSK COGNITIVE MODULATOR FULLY FPGA- 8 IMPLEMENTED VIA DYNAMIC PARTIAL RECONFIGURATION AND RAPID PROTOTYPING TOOLS

IMPLEMENTATION • PR architecture • Basic characteristics: - PR controlled by uBlaze - VHDL coded memory and ADC/DAC controllers. Implementation (4 of 7) - ICAP internal access port - 2 PR implementations OQPSK COGNITIVE MODULATOR FULLY FPGA- 9 IMPLEMENTED VIA DYNAMIC PARTIAL RECONFIGURATION AND RAPID PROTOTYPING TOOLS

IMPLEMENTATION • FPGA partial reconfiguration and rapid prototyping tools  Not a standardized procedure  Possible but potentially dangerous  Necessary steps Implementation (5 of 7)  Extraction of the non-reconfigurable FPGA resources (DCM, BUFG...)  Static and reconfigurable port concordance  Manage properly data exchanges OQPSK COGNITIVE MODULATOR FULLY FPGA- 10 IMPLEMENTED VIA DYNAMIC PARTIAL RECONFIGURATION AND RAPID PROTOTYPING TOOLS

IMPLEMENTATION • Working Algorithm FPGA power up FPGA configuration from platform FLASH • Partial bitstream copy from FLASH to RAM/BRAM Initialization • ICAP initialization Implementation (6 of 7) Read PSD estimator data Analysis & decision Partial reconfiguration New frequency OQPSK COGNITIVE MODULATOR FULLY FPGA- 11 IMPLEMENTED VIA DYNAMIC PARTIAL RECONFIGURATION AND RAPID PROTOTYPING TOOLS

IMPLEMENTATION • Test framework VECTOR SIGNAL ANALYZER MODULATOR DISTURBANCE CHANNEL Implementation (7 of 7) OQPSK COGNITIVE MODULATOR FULLY FPGA- 12 IMPLEMENTED VIA DYNAMIC PARTIAL RECONFIGURATION AND RAPID PROTOTYPING TOOLS

MEASUREMENTS • Resource measurements  Small form factor (<35%) Measurements (1 of 2)  PSD estimator, main resource consumer (data processing) – 10%  uBlaze system, main resource consumer (overall) – 19% OQPSK COGNITIVE MODULATOR FULLY FPGA- 13 IMPLEMENTED VIA DYNAMIC PARTIAL RECONFIGURATION AND RAPID PROTOTYPING TOOLS

MEASUREMENTS • Reconfiguration time measurements Measurements (2 of 2)  ICAP theoretical speed: 400 MBps  Measured speed: 4.5 – 8 MBps  Suboptimal ICAP implementation  Theoretical reconfiguration times below the millisecond OQPSK COGNITIVE MODULATOR FULLY FPGA- 14 IMPLEMENTED VIA DYNAMIC PARTIAL RECONFIGURATION AND RAPID PROTOTYPING TOOLS

CONCLUSIONS AND FUTURE WORK • Conclusions  Simple application but valid as a proof-of-concept  Benefits: resource and power reduction, reliable communications and easy design  Main drawback: reconfiguration time and hand made operations Conclusions and future work • Future work  Develop an optimized own ICAP  Develop a design methodology- reconfigurable function analysis  Framework appliance to a multi-standard modulator OQPSK COGNITIVE MODULATOR FULLY FPGA- 15 IMPLEMENTED VIA DYNAMIC PARTIAL RECONFIGURATION AND RAPID PROTOTYPING TOOLS

QUESTIONS OQPSK COGNITIVE MODULATOR FULLY FPGA- 16 IMPLEMENTED VIA DYNAMIC PARTIAL RECONFIGURATION AND RAPID PROTOTYPING TOOLS