Pulse Injector Board 2-21-2014 Zach Lasiuk 1 Overview FPGA - PowerPoint PPT Presentation

Pulse Injector Board 2-21-2014 Zach Lasiuk 1

Overview FPGA instruction Courtesy of of E. Hazen 2-21-2014 Zach Lasiuk 2

Board Layout DAC Power I2C BUS Buffer (Pulse Height) 3.3V FPGA signals Mezz Card Connectors Pulse Generating Sections Inverters GPIO Expander (Pulse Triggers) (slow, fixed pattern) 2-21-2014 Zach Lasiuk 3

Pulse Low-Pass Voltage Generating filter Divider AND gate Close-Up * The GPIO and trigger signals must both be on for a pulse to be generated. * Since the voltage divider circuit is inverted, we get a very small 'negative' pulse. * One trigger signal can activate/control four pulses. * Charge sent to Mezz Card varies from 0-100fC 2-21-2014 Zach Lasiuk 4

Mezzanine Card Connections *Three different types of Mezz Cards 2-21-2014 Zach Lasiuk 5