PUBLICATION Future Circular Collider, Key Technologies and - PDF document

CERN-ACC-SLIDES-2016-0018 Future Circular Collider PUBLICATION Future Circular Collider, Key Technologies and Challenges Gutleber, Johannes (CERN) et al. 09 August 2016 The research leading to this document is part of the Future Circular Collider Study The electronic version of this FCC Publication is available on the CERN Document Server at the following URL : <http://cds.cern.ch/record/2206394 CERN-ACC-SLIDES-2016-0018

Future Circular Collider Key Technologies and Challenges Johannes Gutleber cern.ch/fcc

EC Strategy Update 2013 undertake design “CERN should studies for accelerator projects in a global context , with emphasis on proton-proton and electron-positron high-energy frontier machines. ”

Conceptual Design Study • Form global collaboration • Study pp/ion collider (FCC-hh) • Infrastructure driven by FCC-hh • Study e + e - collider (FCC-ee) • Understand pe option (FCC-he)

Strategic Goals • Make funding bodies aware of strategic needs for research community • Provide sound basis to policy bodies to establish long-range plans in European interest • Strengthen capacity and effectiveness in high-tech domains • Provide a basis for long-term attractiveness of Europe as research area

HEP Timescale 1980 1985 1990 1995 2000 2005 2010 2015 2020 2025 2030 2035 Upgr LEP Construction Physics LHC Construction Design Proto Physics HL-LHC Design Construct Physics Future Collider Design Proto Construction Physics 25 years Today CDR & Cost

Time Indicator Case: LHC superconducting dipole magnets 1980 1985 1995 2000 2005 2010 1990 Conceptual studies R & D Development Industrialization Series production Industry participation ~ 15 years Total ~ 25 years

Time Indicator Case: PLC (HMI 5-7 yrs, PLC 12 yrs, I/O 16-20 yrs) 1980 1990 2010 2020 2030 2040 2000 SIMATIC S5 Migration SIMATIC S7 cRIO ? OMRON C-Series Hitachi H200 Schneider Mod. 984 Migration “Open” IO Control ?

FCC-hh Key Parameters Parameter FCC-hh LHC Energy [TeV] 100 c.m. 14 c.m. Dipole field [T] 16 8.33 # IP 2 main, +2 4 Luminosity/IP main [cm -2 s -1 ] 5 x 10 34 1 x 10 34 Energy/beam [GJ] 8.4 0.39 Synchr. rad. [W/m/apert.] 28.4 0.17 Bunch spacing [ns] 25 (5) 25 Preliminary, subject to evolution

FCC-ee Key Parameters Parameter FCC-ee LEP2 Energy/beam [GeV] 45 120 175 105 Bunches/beam 16700 1360 98 4 Beam current [mA] 1450 30 6.6 3 Luminosity/IP x 10 34 cm -2 s -1 28 6 1.8 0.0012 Energy loss/turn [GeV] 0.03 1.67 7.55 3.34 Synchr. Power [MW] 100 22 RF Voltage [GV] 2.5 5.5 11 3.5 Preliminary, subject to evolution

Tevatron (closed) Circumference: 6.2 km Energy: 2 TeV

Large Hadron Collider Circumference: 27 km Energy: - 14 TeV (pp) - 209 GeV (e + e - )

Future Circular Collider Circumference: 80-100 km Energy: - 100 TeV (pp) >350 GeV (e + e - ) -

Baseline Layout for Study

Role of CERN • Host the study • Prepare organisation frame • Setup collaboration • Identify R&D needs • Estimate costs

Study Timeline 2014 2015 2016 2017 2018 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Study plan, define scope Explore Review, adjust scope Study Review, select variants Elaborate Review, approve material Report Release CDR

Key Technologies • High-field superconducting magnet • Superconducting RF cavities • Efficient RF power sources • Affordable & reliable cryogenics • Reliability & availability concepts

Special Needs • Collimation systems – High energetic beam • Kickers and separators – Ultra fast systems • Dumps and stoppers – High power absorption

Special Attention • Alignment – Precision survey and alignment – Active systems for FCC-ee • Vacuum – High synchrotron radiation – Mitigate pressure blow-up and electron/ion clouds

Equipment Protection • Fast & scalable • Affordable off-the-shelf • Configurable vs. programmable • Local intelligence • Reliable and maintainable • Fault-tolerant

Fast & Scalable COTS > 100 k channels, > 10 k modules, > 1 k processors Frontend Controller < 5 µsec per value, > 100 values/chassis, > 100 k values 1 k rules / chassis CPU/FPGA chassis CPU/FPGA chassis < 5 µsec, > 200 kHz 2 k channels / chassis IO Module IO Module IO Module IO Module IO Module IO Module IO Module IO Module Analogue IO: Digital IO: Configurable buffer depths, < 200 nsec isochronous data provision, 64-128 channels threshold, trending, deadband

Configurable vs. Programmable • IEC 61131-3 limited for large systems • Any programming language challenging for safety-related systems • Hard-wired functions do not scale • Configurable model permits concentrating on problem domain – Simple rules, which can be analysed – Parallel processing for highest performance – Automatic distribution

Local Intelligence Supervision Frontend Controller CPU/FPGA chassis CPU/FPGA chassis Rules processing (fast for local IO, slower for remote IO) IO Module IO Module IO Module IO Module IO Module IO Module IO Module IO Module Filtering, reduction, alarming, trending

Reliable & Fault Tolerant Software + data configuration management for large systems Frontend Controller Redundant/diverse signal exchange, Support for safety-related data exchange Separation of concerns CPU/FPGA chassis CPU/FPGA chassis (CPU,FPGA), memory protection, self-testing, voting architecture IO Module IO Module IO Module IO Module IO Module IO Module IO Module IO Module Ease of exchange! (Human & robotic) Self-testing, redundant channels, separately powered, galvanically separated, automatic or remote switchover robust signal connection