processes and threads placement of parallel applications
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Processes and Threads Placement of Parallel Applications. Why, How - PowerPoint PPT Presentation

Jun 11, 2023 •174 likes •937 views

Processes and Threads Placement of Parallel Applications. Why, How and for What gain? Joint work with: Guillaume Mercier, Franois Tessier, Brice Goglin, Emmanuel Agulo, George Bosilca. COST spring School, Uppsala Emmanuel Jeannot Runtime

  1. Processes and Threads Placement of Parallel Applications. Why, How and for What gain? Joint work with: Guillaume Mercier, François Tessier, Brice Goglin, Emmanuel Agulo, George Bosilca. COST spring School, Uppsala Emmanuel Jeannot Runtime Team June 4, 2013 Inria Bordeaux Sud-Ouest

  2. 1 Runtime Systems and the Inria Runtime Team Process and Thread Placement July 4, 2012

  3. Software Stack Applications Hardware Process and Thread Placement July 4, 2012

  4. Software Stack Applications Enable and express parallelism Programming models Give abstraction of the parallel machine Hardware Process and Thread Placement July 4, 2012

  5. Software Stack Applications Enable and express parallelism Programming models Give abstraction of the parallel machine Static optimization Compilers Parallelism extraction Hardware Process and Thread Placement July 4, 2012

  6. Software Stack Applications Enable and express parallelism Programming models Give abstraction of the parallel machine Static optimization Compilers Parallelism extraction Optimize Computational Libraries Kernels Hardware Process and Thread Placement July 4, 2012

  7. Software Stack Applications Enable and express parallelism Programming models Give abstraction of the parallel machine Static optimization Compilers Parallelism extraction Optimize Computational Libraries Kernels Operating systems Hardware abstraction Basic services Hardware Process and Thread Placement July 4, 2012

  8. Software Stack Applications Enable and express parallelism Programming models Give abstraction of the parallel machine Static optimization Compilers Parallelism extraction Optimize Computational Libraries Kernels Dynamic optimization Runtime systems Operating systems Hardware abstraction Basic services Hardware Process and Thread Placement July 4, 2012

  9. Runtime System • Scheduling • Parallelism orchestration (Comm. Synchronization) • I/O • Reliability and resilience • Collective communication routing • Migration • Data and task/process/thread placement • etc. Process and Thread Placement July 4, 2012

  10. Runtime Team Inria Team Enable performance portability by improving interface expressivity Success stories: • MPICH 2 (Nemesis Kernel) • KNEM (enabling high-performance intra-node MPI communication for large messages) • StarPU (unified runtime system for CPU and GPU program execution) • HWLOC (portable hardware locality) Process and Thread Placement July 4, 2012

  11. 2 Process Placement June 4, 2013

  12. MPI (Process-based runtime systems) Performance of MPI programs depends on many factors that can be handled when you change the machine: • Implementation of the standard (e.g. collective com.) • Parallel algorithm(s) • Implementation of the algorithm • Underlying libraries (e.g. BLAS) • Hardware (processors, cache, network) • etc. But … June 4, 2013

  13. Process Placement The MPI model makes little (no?) assumption on the way processes are mapped to resources It is often assume that the network topology is flat and hence the process mapping has little impact on the performance Interconection network CPU CPU CPU CPU Mem Mem Mem Mem June 4, 2013

  14. The Topology is not Flat Due to multicore processors current and future parallel machines are hierarchical Communication speed depends on: • Receptor and emitter • Cache hierarchy • Memory bus • Interconnection network etc. Almost nothing in the MPI standard help to handle these factors June 4, 2013

  15. Example on a Parallel Machine The higher we have to go into the hierarchy the costly the data exchange June 4, 2013

  16. Example on a Parallel Machine The higher we have to go into the hierarchy the costly the data exchange Local RAM Mem. Controler L3 Bus L1/L2 L1/L2 L1/L2 L1/L2 Core 1 Core 2 Core 3 Core 4 June 4, 2013

  17. Example on a Parallel Machine The higher we have to go into the hierarchy the costly the data exchange Local RAM Mem. Controler L3 Bus L1/L2 L1/L2 L1/L2 L1/L2 Core 1 Core 2 Core 3 Core 4 June 4, 2013

  18. Example on a Parallel Machine The higher we have to go into the hierarchy the costly the data exchange Local RAM Local RAM Local RAM Mem. Controler Mem. Controler Mem. Controler Interconect L3 L3 L3 Bus L1/L2 L1/L2 L1/L2 L1/L2 L1/L2 L1/L2 L1/L2 L1/L2 Core 1 Core 2 Core 3 Core 4 ... ... Core Core Core Core June 4, 2013

  19. Example on a Parallel Machine The higher we have to go into the hierarchy the costly the data exchange Local RAM Local RAM Local RAM Mem. Controler Mem. Controler Mem. Controler Interconect L3 L3 L3 Bus L1/L2 L1/L2 L1/L2 L1/L2 L1/L2 L1/L2 L1/L2 L1/L2 Core 1 Core 2 Core 3 Core 4 ... ... Core Core Core Core June 4, 2013

  20. Example on a Parallel Machine The higher we have to go into the hierarchy the costly the data exchange Local RAM Local RAM Local RAM Network Mem. Controler Mem. Controler Mem. Controler Interconect NIC NIC L3 L3 L3 Local RAM Local RAM Local RAM Local RAM Bus L1/L2 L1/L2 L1/L2 L1/L2 L1/L2 L1/L2 Mem. Controler Mem. Controler Mem. Controler Mem. Controler L1/L2 L1/L2 Node Node Node Node Core 1 Core 2 Core 3 Core 4 ... ... Core Core Core Core June 4, 2013

  21. Example on a Parallel Machine The higher we have to go into the hierarchy the costly the data exchange Local RAM Local RAM Local RAM Network Mem. Controler Mem. Controler Mem. Controler Interconect NIC NIC L3 L3 L3 Local RAM Local RAM Local RAM Local RAM Bus L1/L2 L1/L2 L1/L2 L1/L2 L1/L2 L1/L2 Mem. Controler Mem. Controler Mem. Controler Mem. Controler L1/L2 L1/L2 Node Node Node Node Core 1 Core 2 Core 3 Core 4 ... ... Core Core Core Core June 4, 2013

  22. Example on a Parallel Machine The higher we have to go into the hierarchy the costly the data exchange Local RAM Local RAM Local RAM Network The network can also be Mem. Controler Mem. Controler Mem. Controler Interconect NIC NIC hierarchical! L3 L3 L3 Local RAM Local RAM Local RAM Local RAM Bus L1/L2 L1/L2 L1/L2 L1/L2 L1/L2 L1/L2 Mem. Controler Mem. Controler Mem. Controler Mem. Controler L1/L2 L1/L2 Node Node Node Node Core 1 Core 2 Core 3 Core 4 ... ... Core Core Core Core June 4, 2013

  23. Rationale Not all the processes exchange the same amount of data The speed of the communications, and hence performance of the application depends on the way processes are mapped to resources. June 4, 2013

  24. Do we Really Care: to Bind or not to Bind? After all, the system scheduler is able to move processes when needed. Yes, but only for shared memory system. Migration is possible but it is not in the MPI standard (see charm++) Moreover binding provides better execution runtime stability. June 4, 2013

  25. Do we Really Care: to Bind or not to Bind? After all, the system scheduler is able to move processes when needed. Yes, but only for shared memory system. Migration is possible but it is not in the MPI standard (see charm++) Moreover binding provides better execution runtime stability. Zeus MHD Blast. 64 Processes/Cores. Mvapich2 1.8. + ICC June 4, 2013

  26. Process Placement Problem Given : • Parallel machine topology • Process affinity (communication pattern) Map processes to resources (cores) to reduce communication cost: a nice algorithmic problem: • Graph partitionning (Scotch, Metis) • Application tuning [Aktulga et al. Euro-Par 12] • Topology-to-patten matching (TreeMatch) June 4, 2013

  27. Reduce Communication Cost? But wait, my application is compute-bound! Well, but this might not be still true in the future: strong scaling might not always be a solution. June 4, 2013

  28. Reduce Communication Cost? But wait, my application is compute-bound! Well, but this might not be still true in the future: strong scaling might not always be a solution. Taken from one of J. Dongarra’s Talk. June 4, 2013

  29. How to bind Processes to Core/Node? MPI standard does not specify process binding Each distribution has its own solution: • MPICH2 (hydra manager): mpiexec -np 2 -binding cpu:sockets • OpenMPI: mpiexec -np 64 -bind-to-board • etc. You can also specify process binding using numactl or taskset unix command in the mpirun command line: mpiexec -np 1 –host machine numactl --physcpubind=0 ./prg June 4, 2013

  30. Obtaining the Topology (Shared Memory) HWLOC (portable hardware locality): • Runtime and OpenMPI team • Portable abstraction (across OS, versions, architectures, ...) • Hierarchical topology • Modern architecture (NUMA, cores, caches, etc.) • ID of the cores • C library to play with • Etc June 4, 2013

  31. HWLOC http://www.open-mpi.org/projects/hwloc/ June 4, 2013

  32. Obtaining the Topology (Distributed Memory) Not always easy (research issue) MPI core has some routine to get that Sometime requires to build a file that specifies node adjacency June 4, 2013

  33. Getting the Communication Pattern No automatic way so far … Can be done through application monitoring: • During execution • With a « blank execution » June 4, 2013

  34. Results 64 nodes linked with an Infiniband interconnect (HCA: Mellanox Technologies, MT26428 ConnectX IB QDR). Each node features two Quad-core INTEL XEON NEHALEM X5550 (2.66 GHz) processors. June 4, 2013

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