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POLYMORPHIC ON-CHIP NETWORKS Martha Mercaldi Kim, John D. Davis*, - PowerPoint PPT Presentation

Oct 20, 2022 •322 likes •1.01k views

POLYMORPHIC ON-CHIP NETWORKS Martha Mercaldi Kim, John D. Davis*, Mark Oskin, Todd Austin** University of Washington *Microsoft Research, Silicon Valley ** University of Michigan On-Chip Network Selection 2 Talk Outline Network-on-chip

  1. POLYMORPHIC ON-CHIP NETWORKS Martha Mercaldi Kim, John D. Davis*, Mark Oskin, Todd Austin** University of Washington *Microsoft Research, Silicon Valley ** University of Michigan

  2. On-Chip Network Selection 2

  3. Talk Outline • Network-on-chip Design Space Exploration • Networks • Workloads • Results • Polymorphic On-Chip Networks • Fabric design • Configuring the network • Selecting a fabric • Evaluation of flexibility • Conclusions • Future Directions 3

  4. On-Chip Network Design Space } { 16 nodes 64 nodes 256 nodes 1024 nodes 4

  5. On-Chip Network Design Space { 16 nodes, 64 nodes, 256 nodes, 1024 nodes } x { } mesh ring fat-tree butterfly flattened- butterfly 4

  6. On-Chip Network Design Space { 16 nodes, 64 nodes, 256 nodes, 1024 nodes } x { mesh, ring, fat-tree, butterfly, flattened-butterfly } x { minimal, oblivious, source-routing } x 4

  7. On-Chip Network Design Space { 16 nodes, 64 nodes, 256 nodes, 1024 nodes } x { mesh, ring, fat-tree, butterfly, flattened-butterfly } x { minimal, oblivious, source-routing } x { } wormhole store-and-forward 4

  8. On-Chip Network Design Space { 16 nodes, 64 nodes, 256 nodes, 1024 nodes } x { mesh, ring, fat-tree, butterfly, flattened-butterfly } x { minimal, oblivious, source-routing } x { wormhole, store-and-forward } x { } 32 bits 64 bits 128 bits 4

  9. On-Chip Network Design Space { 16 nodes, 64 nodes, 256 nodes, 1024 nodes } x { mesh, ring, fat-tree, butterfly, flattened-butterfly } x { minimal, oblivious, source-routing } x { wormhole, store-and-forward } x { 16 bits, 64 bits, 128 bits } x { } 4 entries 16 entries 64 entries 4

  10. On-Chip Network Design Space { 16 nodes, 64 nodes, 256 nodes, 1024 nodes } x { mesh, ring, fat-tree, butterfly, flattened-butterfly } x { minimal, oblivious, source-routing } x { wormhole, store-and-forward } x { 16 bits, 64 bits, 128 bits } x { 4 entries, 16 entries, 64 entries } = 360 on-chip networks 4

  11. On-Chip Network Design Space { 16 nodes, 64 nodes, 256 nodes, 1024 nodes } x { mesh, ring, fat-tree, butterfly, flattened-butterfly } x { minimal, oblivious, source-routing } x { wormhole, store-and-forward } x { 16 bits, 64 bits, 128 bits } x { 4 entries, 16 entries, 64 entries } = 360 on-chip networks cycle-level software simulator 4

  12. Network Traffic Patterns { } Uniform Nearest Random Random Neighbor Permutation (injection rate = 1 packet / cycle) 5

  13. Network Measurements: Random Permutation (Random Permutation) 6

  14. Network Measurements: Random Permutation throughput-sensitive application (Random Permutation) 6

  15. Network Measurements: Random Permutation throughput-sensitive application (Random Permutation) latency-sensitive application 6

  16. Network Measurements (Random Permutation) (Uniform Random) (Nearest Neighbor) 7

  17. Talk Outline • Network-on-chip Design Space Exploration • Networks • Workloads • Results • Polymorphic On-Chip Networks • Fabric design • Configuring the network • Selecting a fabric • Evaluation of flexibility • Conclusions • Future Directions 8

  18. The Intuition... 9

  19. The Intuition... 9

  20. The Intuition... mesh 9

  21. The Intuition... mesh 9

  22. The Intuition... mesh 9

  23. The Intuition... mesh ring 9

  24. The Intuition... fat tree mesh ring 9

  25. Polymorphic On-Chip Network What it is • Sea of structures all networks have in common • Configurable connections between structures How it is used • Gather structures to arbitrary-degree switches • Connect switches input and output ports 10

  26. Talk Outline • Network-on-chip Design Space Exploration • Networks • Workloads • Results • Polymorphic On-Chip Networks • Fabric design • Configuring the network • Selecting a fabric • Evaluation of flexibility • Conclusions • Future Directions 11

  27. Configuring the Network 1.Switch degree 2.Inter-switch connections 3.Packet width 4.Buffer capacity 12

  28. Configuring the Network 1.Switch degree configurable topology 2.Inter-switch connections 3.Packet width 4.Buffer capacity 12

  29. Configuring the Network 1.Switch degree configurable topology 2.Inter-switch connections 3.Packet width configurable resource allocation 4.Buffer capacity 12

  30. Network Configuration: Switch Degree 1.Switch degree 13

  31. Network Configuration: Switch Degree 1.Switch degree 13

  32. Network Configuration: Switch Degree 1.Switch degree 13

  33. Network Configuration: Switch Degree 1.Switch degree 13

  34. Internal Configuration of a Switch 14

  35. Internal Configuration of a Switch 14

  36. Internal Configuration of a Switch 14

  37. Internal Configuration of a Switch 14

  38. Internal Configuration of a Switch 14

  39. Internal Configuration of a Switch 14

  40. Internal Configuration of a Switch 14

  41. Internal Configuration of a Switch 14

  42. Network Configuration: Links 1.Switch degree 2.Inter-switch connections 15

  43. Network Configuration: Packet Width 1.Switch degree 2.Inter-switch connections 3.Packet width 16

  44. Network Configuration: Queue Capacity 1.Switch degree 2.Inter-switch connections 3.Packet width 4.Buffer capacity 17

  45. An Example: Configuration of a Mesh 18

  46. An Example: Configuration of a Mesh 18

  47. An Example: Configuration of a Mesh 18

  48. An Example: Configuration of a Mesh 18

  49. An Example: Configuration of a Mesh 18

  50. An Example: Configuration of a Mesh 18

  51. Talk Outline • Network-on-chip Design Space Exploration • Networks • Workloads • Results • Polymorphic On-Chip Networks • Fabric design • Configuring the network • Selecting a fabric • Evaluation of flexibility • Conclusions • Future Directions 19

  52. Polymorphic Fabric Parameter Space queue width and depth no. vertical routing wires resources per cluster no. horizontal routing resources 20

  53. Polymorphic Fabric Parameter Space W = {32, 64, 128} D = {4, 16, 64} V = {N, 2N} N = {2, 4, 8, 16} H = {N, 2N} 21

  54. Polymorphic Fabric Area Overhead ASIC implementation Polymorphic implementation 22

  55. Polymorphic Fabric Area Overhead ASIC implementation Polymorphic implementation Area as ASIC 22

  56. Polymorphic Fabric Area Overhead ASIC implementation Polymorphic implementation Area in Polymorphic Fabric Area as ASIC 22

  57. Polymorphic Fabric Area Overhead ASIC implementation Polymorphic implementation Area in Polymorphic Fabric Area Overhead = Area as ASIC 22

  58. Polymorphic Fabric Area Overhead ASIC implementation Polymorphic implementation Area in Polymorphic Fabric Area Overhead = Area as ASIC 22

  59. Polymorphic Fabric Area Overhead ASIC implementation Polymorphic implementation Area in Polymorphic Fabric Area Overhead = Area as ASIC 22

  60. Area Overhead of Polymorphic Fabrics 144 polymorphic fabrics Area efficient networks have small queues and generous routing resources 23

  61. Polymorphic Fabric Parameter Space W={32, 64, 128} D = {4, 16, 64} V = {N, 2N} N = {2, 4, 8, 16} H = {N, 2N} 24

  62. Talk Outline • Network-on-chip Design Space Exploration • Networks • Workloads • Results • Polymorphic On-Chip Networks • Fabric design • Configuring the network • Selecting a fabric • Evaluation of flexibility • Conclusions • Future Directions 25

  63. Network Selection Under Area Budget 2 Of networks smaller than 22 mm , 26 are pareto optimal. 26

  64. Network Selection Under Area Budget 2 24 of the 26 optimal networks will fit in 22 mm of polymorphic fabric. 27

  65. Network Selection Under Area Budget Polymorphic coverage is strong for all but the tightest area budgets. 28

  66. Conclusion Widely varying on-chip communication patterns can take advantage of a flexible on-chip network. Polymorphic fabric is a coarse grained reconfigurable circuit designed to implement packet-switched networks on chip. Subject to area budget, polymorphic fabric usually offers broad choice of network. Should build polymorphic network unless 1. Area budget highly constrained 2. Application and/or traffic not expected to vary 29

  67. Some Future Directions 1. Hardware implementation 2. Uses beyond application performance (e.g., on-chip isolation) 3. Incorporation of advanced on-chip network innovations 4. Reconfiguration policy 30

  68. THANK YOU

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