PMT driver status update 2 Continuation from presentation 2 weeks - PowerPoint PPT Presentation

10/26/17 1 1 PMT driver status update

2 Continuation from presentation 2 weeks ago:

3 What is the current status? ● Circuit design – finished ● PCB design – finished ● Final design review – in progress ● Enclosure design – in progress ● PCB manufacturing – to begin when review passes ● Assembly – to begin when components and PCB arrive ● Testing and debugging – not started

4 PMT driver specifications ● PMT power (15V) and individual PMT gain adjustment. Designed for Hamamatsu H10425 Series. ● Four input channels. ● Per PMT input channel: ● Amplifier with 6mV per 1uA gain, 350MHz bandwidth. ● Pulse height discriminator with adjustable discriminator level (0 - 3.3V) and adjustable constant length pulse output (20ns – 5us). Timing jitter on the order of 100ps. ● Precise trigger pulse output as LVDS pair over cat5 Ethernet cable. ● Trigger pulses go through optional delay line and are combined through programmable logic. ● Combined trigger pulse is output as TTL and LVDS.

5 Schematic overview

6 PMT signal input Pulse height discriminator Programmable logic Adjustable threshold ● Amplifier Outputs low timing accuracy Adjustable output pulse duration ● trigger pulse (~±10ns) Optional delay line LVDS trigger pulse TTL trigger pulse High timing accuracy pulses (~±200ps) output over cat5 cable

7 PMT signal input Pulse height discriminator Programmable logic Adjustable threshold ● Amplifier Outputs low timing accuracy Adjustable output pulse duration ● trigger pulse (~±10ns) Optional delay line LVDS trigger pulse TTL trigger pulse High timing accuracy pulses (~±200ps) output over cat5 cable

8 PMT signal input Pulse height discriminator Programmable logic Adjustable threshold ● Amplifier Outputs low timing accuracy Adjustable output pulse duration ● trigger pulse (~±10ns) Optional delay line LVDS trigger pulse TTL trigger pulse High timing accuracy pulses (~±200ps) output over cat5 cable

9 PMT signal input Pulse height discriminator Programmable logic Adjustable threshold ● Amplifier Outputs low timing accuracy Adjustable output pulse duration ● trigger pulse (~±10ns) Optional delay line LVDS trigger pulse TTL trigger pulse High timing accuracy pulses (~±200ps) output over cat5 cable

10 Programmable logic

11 22cm 16cm

Amplifier chain overview Buffer Buffer Buffer Coaxial input Inverting amplifier Noninverting amplifier Terminated to 50Ω 21.6 dB 20.2 dB

A few details about high frequency amplifier circuit design Vias along signal lines. Digital ground plane Provides easy return path for high Possibly noisy frequency current. Arises from capacitive Analog ground plane coupling between signal line and ground Quiet planes. Ground plane cutouts. Decoupling capacitor Decoupling inductors. Reduces stray capacitance on close to amplifier output. Prevents high frequency signals from amplifier inputs. Very sensitive, a Minimizes return current path propagating on the power rails. These can few pF can lead to instabilities. length and current loop area. couple into other amplifiers, creating positive feedback, instabilities, crosstalk, and ringing.

Medium frequency High frequency

15 Planned work: ● Submit design for manufacturing ● Order components ● Assemble ● Test and debug Design available on github: https://github.com/nup002/pmt_driver

16 Thanks!

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