PLESIOCHROUNOUS DIGITAL HIERARCHY ETI 2506 – TELECOMMUNICATION SYSTEMS Monday, 14 November 2016
LINKING DIGITAL TELEPHONE EXCHANGES Clock THIKA Generator 30 Channel PCM – E1 30 Channel PCM – E1 30 Channel PCM-E1 NAKURU NAIROBI MOMBASA Clock Clock Clock Generator Generator Generator DESIGN ISSUES IN DIGITAL TRANSMISSION SYSTEMS 1. How to ensure that the clock generators are synchronized 2. How to support more traffic, i.e > 30 channels
PLESIOCHRONOUS SYSTEM Plesiochronous telecommunication system is one where different parts of the system are almost, but not quite, perfectly synchronised. Clock THIKA Generator 2.048,000 ±5 𝑞𝑞𝑛 30 Channel PCM – E1 30 Channel PCM – E1 30 Channel PCM-E1 NAKURU NAIROBI MOMBASA 2.048,000 ±3 𝑞𝑞𝑛 2.048,000 ±2 𝑞𝑞𝑛 2.048,000 ±4 𝑑𝑞𝑡 Clock Clock Clock Generator Generator Generator
PDH MULTIPLEX SYSTEM - NORTH AMERICA 1. The 24 channel PCM system (T1) is the primary order of Digital Multiplex System. 2. If it is necessary to transmit more than 24 channels, the system is build- up as in the “ Plesiochronous Digital Hierarchy (PDH)”
PDH MULTIPLEX SYSTEM - NORTH AMERICA EO-1 EO-2 T 1 ASC 274.176 Mbits/s T 1 T 2 = 4T 1 1 T 1 Six 44.736 Mb/s T 1 T4 MUX inputs EO-4 6 E0-3 1 Seven 6.312 T3 MUX Mb/s inputs 7 44.736 Mbits/s 1 Four 1.544Mb/s T2 MUX 6.312 Mbits/s Inputs 4 Twenty Four 64 kb/s inputs 1 TI MUX 24 1.544 Mb/s 64kb/s
PDH MULTIPLEX SYSTEM - NORTH AMERICA 1. Second order multiplexing (T2): Four primary systems (24-channle each) are combined, multiplexed, to form an output having 96 channels. 2. Third order Multiplexing (T3): Seven 96 channel systems are multiplexed to give an output of 672- channels. Fourth order Multiplexing (T4): Six 672 – channels 3. systems are multiplexed to give an output of 4032 channels -
SECOND ORDER - DS2 PDH (1.544 TO 6.312 MB/S) 1. The 6.312-Mb/s output of a second order ( DS2 ) Multiplexer is created by multiplexing four first order ( DS1 ) multiplexing outputs. 2. This is done by interleaving the bit stream of the four primary systems. 3. Each individual bit stream is called the “ tributary” . 1 T2 MUX 6.312 Mbits/s 4 Four tributaries DS2 each at 1.544 Mb/s
EUROPEAN PDH 138.264 Mbits/s 1 Four 34.368Mbits/s E4 MUX Inputs 4 1 Four E3 MUX 8.44Mbits/s Inputs 4 34.368 Mbits/s 1 Four 2.048Mbits/s E2 MUX 8.44 Mbits/s Inputs 4 Thirty two 64 kb/s inputs 1 E1 MUX 32 2.048 Mb/s 64kb/s
INTERLEAVING The multiplexing of several tributaries can be achieved a) Bit by bit multiplexing, i.e bit interleaving b) Word by word multiplexing or byte interleaving
COMPARISON OF BIT AND BYTE INTERLEAVING Byte interleaving sets some restraints on the frame structure of the tributaries and require more memory storage. Bit interleaving is much simpler because it is independent of frame structure and also requires less memory capacity.
APPLICATION OF BIT INTERLEAVING 1. Bit interleaving is used in T1 and E1 systems. 2. A typical 6.312 Mb/s plesichronous multiplexer has four primary (DS1) MUX, each having an output of 1.544 Mb/s, bit interleaved to form the next level in hierarchy. 3. Note that this output rate of 6.312 Mb/s is not exactly four times the tributary bit rate of 1.544 Mb/s.
BIT STUFFING IN PDH Bit stuffing (also called positive justification) is the insertion of non information bits into data. Bit stuffing is used in PDH to account for the small variations of the tributaries data rates about the nominal value.
PDH MUX Europe In summary, the positive stuffing method involves the canceling of a clock pulse assigned to a particular tributary in some of the frames in order to coordinate the timing of the plesiochronous tributaries into a multiplexed output. Random spaces are therefore created in the frame, as well as periodic spaces. In the periodic spaces frame alignment word bits service bits, and stuffing control bits are inserted. The tributary information bits are inserted in the random spaces in the absence of stuffing, or logic 1 is used when stuffing taken place.
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