Platform- -Based Synthesis for Based Synthesis for Platform Field - PDF document

Platform- -Based Synthesis for Based Synthesis for Platform Field Field- -Programmable Programmable SOCs SOCs Prof. Jason Cong Prof. Jason Cong cong@cs.ucla.edu cong@cs.ucla.edu UCLA Computer Science Department UCLA Computer Science Department Outline Outline Motivation � Motivation � xPilot system framework system framework � xPilot � Behavior- -level synthesis in level synthesis in xPilot xPilot � Behavior � � � Advantages of behavioral synthesis Advantages of behavioral synthesis � Scheduling � Scheduling � Resource binding � Resource binding System- -level synthesis in level synthesis in xPilot xPilot � System � � � Synthesis for ASIP platforms Synthesis for ASIP platforms � Design exploration for heterogeneous � Design exploration for heterogeneous MPSoCs MPSoCs � Conclusions Conclusions � Page 1

Field- -Programmable Programmable SOCs SOCs are Here: are Here: Altera Altera Stratix Stratix II FPGA II FPGA Field Nios II /f Soft core µ Proc 185MHz < 900ALMs (<1800LEs) 90nm Stratix II 2S60 218 Max DMIPS I/O Channels with External Memory Adaptive Logic Interface Circuitry Modules Nios II High-Speed I/O IP Channels with M512 Block DPA Avalon™ Bus Digital Signal Processing (DSP) Blocks M4K Block M-RAM Blocks High-Speed I/O Software defined radio (SDR) Channels with IP Dynamic Phase baseband data path reconfiguration Alignment (DPA) Nios II I/O Channels with Phase-Locked External Memory Loops (PLL) Interface Circuitry 60,440 Equivalent Logic Elements Courtesy Altera Altera Courtesy 2,544,192 Memory Bits Field- Field -Programmable Programmable SOCs SOCs are Here: are Here: Xilinx Xilinx Virtex Virtex- -4 FPGA 4 FPGA MicroBlaze 180MHz Soft core µ Proc < ~1300 LUTs 166 DMIPS IBM CoreConnect™ Bus Micro- IP Blaze IP H.264/AVC hardware blocks PowerPC 405 (PPC405) core 450 MHz, 700+ DMIPS RISC core (32-bit Harvard architecture) Courtesy Xilinx Xilinx Courtesy Page 2

What about FP- -SOC Design Tools SOC Design Tools What about FP Synthesis � Synthesis � � Behavior � Behavior- -level synthesis: from behavior specification (e.g. C, level synthesis: from behavior specification (e.g. C, SystemC SystemC, or , or Matlab Matlab) to RTL or ) to RTL or netlists netlists � � System System- -level synthesis: from system specification to system level synthesis: from system specification to system implementation implementation Verification � Verification � � � Behavior Behavior- -level verification level verification � � System System- -level verification level verification ESL Tools – – A Lot of Interests A Lot of Interests … … ESL Tools Page 3

GartnerDataquest’ ’s s ESL Landscape, 2005 ESL Landscape, 2005 GartnerDataquest xPilot: Platform- -Based Based Synthesis System Synthesis System xPilot: Platform Platform Description Platform Description SystemC/C SystemC /C & Constraints & Constraints xPilot xPilot Front End xPilot Front End Profiling SSDM Analysis (System-Level Synthesis Data Model) Mapping Processor & Interface Behavioral Synthesis Architecture Synthesis Synthesis Custom Logic Processor Cores Drivers + Glue Logic + Executables FPSoC � Uniqueness of Uniqueness of xPilot xPilot � � � Platform Platform- -based synthesis and optimization based synthesis and optimization � � Communication Communication- -centric synthesis with interconnect optimization centric synthesis with interconnect optimization Page 4

Outline Outline Motivation � Motivation � xPilot system framework system framework � xPilot � Behavior- -level synthesis in level synthesis in xPilot xPilot � Behavior � � Advantages of behavioral synthesis � Advantages of behavioral synthesis � Scheduling � Scheduling � Resource binding � Resource binding System- -level synthesis in level synthesis in xPilot xPilot � System � � Synthesis for ASIP platforms � Synthesis for ASIP platforms � Design exploration for heterogeneous � Design exploration for heterogeneous MPSoCs MPSoCs � Conclusions Conclusions � Motivation (1) Motivation (1) Design complexity is outgrowing the traditional RTL � Design complexity is outgrowing the traditional RTL � method method − a critical technology for enabling the Behavioral synthesis − � Behavioral synthesis � a critical technology for enabling the move to higher level of abstraction move to higher level of abstraction � Reasons for previous failures � Reasons for previous failures • Lack of a compelling reason: design complexity is still manageab • Lack of a compelling reason: design complexity is still manageable a le a decade of ago decade of ago • Lack of a solid RTL foundation • Lack of a solid RTL foundation • Lack of consideration of physical reality • Lack of consideration of physical reality Page 5

Motivation (2) Motivation (2) Behavioral synthesis provides combined advantages � Behavioral synthesis provides combined advantages � � � Shorter verification/simulation cycle Shorter verification/simulation cycle � � Better complexity management, faster time to market Better complexity management, faster time to market � � Rapid system exploration Rapid system exploration • Quick evaluation of different hardware/software boundaries • Quick evaluation of different hardware/software boundaries • Fast exploration of multiple micro • Fast exploration of multiple micro- -architecture alternatives architecture alternatives � � Higher quality of results Higher quality of results • Platform • Platform- -based synthesis & optimization based synthesis & optimization • Full consideration of physical reality • Full consideration of physical reality − Better Complexity Management Advantages − Better Complexity Management Advantages � Shorter verification/simulation cycle Shorter verification/simulation cycle � � � Simulation speed 100X faster than RTL Simulation speed 100X faster than RTL- -based method based method [NEC, ASPDAC04] [NEC, ASPDAC04] � Significant code size reduction Significant code size reduction � � � RTL design ~300KL RTL design ~300KL � � Behavioral design 40KL [NEC, ASPDAC04] Behavioral design 40KL [NEC, ASPDAC04] � � VHDL code generated by UCLA xPilot targeting Altera Altera Stratix platform Stratix platform VHDL code generated by UCLA xPilot targeting � � Over 10x code size reduction can be achieved Over 10x code size reduction can be achieved Page 6

− Rapid System Exploration (1) Advantages − Rapid System Exploration (1) Advantages Quick evaluation of various amounts of process level � Quick evaluation of various amounts of process level � concurrency and different hardware/software boundaries concurrency and different hardware/software boundaries Example: Motion-JPEG implementation - All HW implementation - All SW implementation (using embedded processors) - SW/HW co-design: optimal partitioning? - Repeated manual RTL coding is not solution! − Rapid System Exploration (2) Advantages − Rapid System Exploration (2) Advantages � Fast exploration of multiple micro Fast exploration of multiple micro- -architecture alternatives architecture alternatives � � � Different hardware implementations can be easily obtained by Different hardware implementations can be easily obtained by varying the high- -level spec. and applying different design level spec. and applying different design varying the high constraints constraints Target cycle time Target cycle time State# State# Fmax (MHz) Fmax (MHz) Cycle# Cycle# Latency (ns) Latency (ns) LE# LE# DSP# DSP# 9ns 34 123.56 4830 39.1 1777 128 9ns 34 123.56 4830 39.1 1777 128 7ns 7ns 36 36 147.28 147.28 5211 5211 35.4 35.4 1862 1862 128 128 5.5ns 5.5ns 51 51 183.62 183.62 6926 6926 37.8 37.8 1926 1926 128 128 � � Platform: Altera Altera Stratix Stratix Platform: � � RTL synthesis & place- -and and- -route: route: Altera Altera QuartusII QuartusII v5.0 v5.0 RTL synthesis & place � � Simulation: Mentor ModelSim ModelSim SE6.0 SE6.0 Simulation: Mentor Page 7