Platform-Based Co-Design and Co-Development: Experience, Methodology and Trends Grant Martin and Jean-Yves Brunel Cadence Berkeley and Paris Electronic Design Processes Workshop, Monterey, April 21-23, 2002 1 CADENCE DESIGN SYSTEMS, INC. Outline • Design Flows • Automotive ‘Software-Software’ codesign • Multimedia Design Space Exploration • Conclusions 2 1
Embedded System Development Application Architecture Application Architecture Modelling Modelling Modelling Modelling Emphasised in Design Space Platform Design Space Development Exploration Exploration Links to Links to Implementation Implementation Emphasised in Derivative Co-Verification Co-Verification Design 3 Distributed Automotive Applications over networks – “Software-Software Codesign” • Electronic Control Units (ECU’s) • Standard buses (TTP, CAN, FlexRay) • Standard Platforms 2
Current Design Practices Requirements Requirements analysis analysis Matlab Matlab Engine Control “functional network” f1 f1 f2 f2 specification specification Development process ASCET ASCET f3 “zero time assumption” f3 f4 f4 Gear-Box Control system design system design “real world assumption” ECU- -1 1 ECU ECU ECU- -2 2 CAN/TTP- CAN/TTP -bus bus implementation implementation ECU- -3 3 “automatic target code gen.” ECU .c .c .c ... Architecture Architecture integration & calibration integration & calibration .c .c .c ... “step into a real car” production & after sales production & after sales “handling at the garage” • Integration is done too late In the car • Tools are PER-ECU – conservative, costly, no tradeoffs 5 Virtual Integration Platform for Distributed Automotive Applications Software Components Architectural Models IP’s C-Code Buses CPUs Buses Buses Operating Matlab C++ Systems Analysis Development Process System Behavior System Architecture Specification f1 f1 f2 f2 ASCET f3 f3 Evaluation of Mapping Architectural Implementation and ASCET Performance Partitioning Simulation Alternatives Calibration Refinement After Sales Service V C C V C C 6 3
Scenarios for SW-driven co-development f f f f f f f f f ?? ?? f f f f f f f f f f f f ?? f f f f f f 7 ASCET-SD imported project in VCC Message1 Message2 Message3 Message4 Interrupt IntrptReceiveTask1 These are behavioral memories HWIntrp HW_Intrpt1 HWIntrpt1 Timer10msec TestBench ProjectA Timer10msec Interrupt These are behavioral HWIntrpt SWIntrpt These are behavioral HW_Intrpt2 HWIntrpt2 memories HWIntrpt SWIntrpt memories ReceiveSendTask5 IntrptSendTask1 ReceiveSendTask5 ReceiveSendTask3 GlobalVariable ReceiveSendTask1 ReceiveSendTask3 GlobalVariable ReceiveSendTask1 The test-bench can include Matlab imported models This is the ASCET imported Project as well as VCC authored models Timer20ms SW_Interrupt1 SW_Interrupt1 Timer20ms SW_Interrupt1 SW_Interrupt1 HWIntrpt1 HW_Interrupt1 HWIntrpt1 HW_Interrupt1 Module0 Module2 Module0 Module2 ReceiveSendTask6 ReceiveSendTask6 Process8 SW_Interrupt2 SW_Interrupt2 SW_Interrupt2 SW_Interrupt2 SW_Interrupt Timer30ms Timer30ms HWIntrpt2 HW_Interrupt SW_Interrupt These are the processes These are the modules HWIntrpt2 HW_Interrupt Module1 SW_Interrupt These are the processes for the protected These are the modules Module1 of the ASCET project for the protected HW_Interrupt variables of the ASCET project Process9 variables GlobalVariable2 GlobalVariable2 These are behavioral These are behavioral timers timers HWIntrpt SWIntrpt HWIntrpt SWIntrpt Process10 ReceiveSendTask7 ReceiveSendTas ReceiveSendTask7 ReceiveSendTask4 ReceiveSendTas ReceiveSendTask4 8 4
Universal Communications Model of Bus Behavioral Diagram Behavioral Memory 1 Module A Module B ECU 1 ECU 1 RTOS RTOS PPC PPC internal bus internal bus Architectural Mem Bus Memory Mem Bus Bus Controller Controller Peak Load Broadcast Bus Example Design Flow (1): Power Window • Definition of a behavioral diagram: Import of functional components (software projects and modules) BrakeSwitchFil BTSetUp Ti m er Aquire S ig nal pul at M ani or Br akeO ut F L Base Brake & ABS Br ake O ut FR A quireSignal PedalSensor1Fil M an at o r i pul PedalSensor2Fil quireSignal A O ut Br ake R L PedalSensor3Fil M an r at o i pul A quireSignal R R ut Br akeO Hand BrakeSwitchFil M an i pul r at o A quireSignal ClampFo rceFLFil quireSignal A ClampForceFRFil quireSignal A ClampFo rceRLFil quireSignal A Base Steering ClampForceRRFil St ee ngO ut 1 r i M an i pul at o r quireSigna A l St ee r i ngO ut 2 SteeringWh eelAngle1Fil M an r at o i pul quireSigna A l BrakeSwitch Steerin gWheelAngle2Fil PedalSensor1 quir e A Signal PedalSensor2 Steerin gWheelAngle3Fil quir e A Signal fo rm Uni Pul se s Un iform PedalSensor3 Pu iform lses Un Pu lses Steerin gWheelAngle4Fil HandBrakeSwitch quir e A Signal ClampForceFL RackPosition1Fil A quireSignal ClampForceFR Handwheel ClampFo rceRL RackPosition2Fil Feedback Wheel i ng St eer Tor queO ut 1 ni pul M a at or quireSignal A ClampFo rceRR Tr i ger BrakeAc tuator RackPosition3Fil Br a keA ct uat or O ut quireSignal A Steerin gWheelAngle1 Wheel i ng St eer Tor queO ut 2 Tr i gger M an i pul at o r Steering WheelAngle2 RackPosition4Fil Tr i gger Aquire S ig nal DbW_TopBlock Brak eActu ator Steering WheelAngle3 uat o Br akeA ct ut r O Steerin gWheelAngle4 Tr i gg er Steering WheelTor que1Fil D r i ver St eer D r i ve r r St ee 2 Track RackPosition1 Tr i gger A quireSignal Driver Brak ator eActu ver r i D Br ake Vehicle RackPosition2 ct Br akeA uat o r O ut ver Br a r i D ke Steering WheelTor que2Fil i ve r G D r as Model quireSignal A D r i ver G as RackPosition3 M er 1Br a ast keFL r Cl ut i ve D r ch D r i ver C l ch ut RackPosition4 Tr i ger BrakeAc tuator quireSignal A Steering WheelTor que3Fil ver G r i D ear Br a keA ct uat ut or O M a st er 1Br ake F R i ver D r ar G e Steering WheelTorqu e1 er 1Br a ast M keRL Steering WheelTorqu e2 i gger Tr Ste erActua tor TieRodForce1Fil ast M er 1Br a keRR Steering WheelTorqu e3 eer St uat A ct or O ut Aquire S ig nal Master M as 1S t t er eO ngl i ngA eer ut TieRodForce1 TieRodForce2Fil Aquire S ig nal Controller keA Br a ct uat or FR TieRodForce2 Tr i ger SteerAct uator M ast er 1St eer i ngTor qu eO ut St eer A ct uat or O ut TieRodForce3Fil keA Br a or FL ct uat vel _veh_m er _1 ast TieRodForce3 Aquire S ig nal keA Br a ct uat or RL M ast er 1W ng ar ni Br a keA ct uat or RR Speed FL andW H T o heel r queA ct u at or SpeedFLFil Br ake D i agnosi s ngA eer i St t or 2 ct ua SpeedFR Aquire S ig nal ngA eer i St t or ct ua 1 H andW T o heel r queA ct u at or Speed RL SpeedFRFil er 2Br M ast akeFL Aquire S ig nal eedRR Sp ast M er 2Br a keFR i ngD St eer s agnosi i YawRate ar ni W ngLi ght el l ow Y SpeedRLFil Master Aquire S ig nal M ast er 2Br akeRL Later alAcceleration Speed RRFil Controller er 2 M ast akeRR B r W ar ni ngLi ght Y el l ow Aquire S ig nal M a 2St ee st er eO r i ng A ngl ut CurrentBatterie1 edbackD WFe H i a gnosi s Un ifor m ngLi War ni ght Red lse s Pu YawRateFil M as i ngTor 2St eer t er ut queO gger Tr i VoltageBatterie1 quireSigna A l CurrentBatterie2 ni ngLi War ght Red LateralAccelerationFil v el _ve h_m as t er _2 BordnetStimulator A quireSignal VoltageBatterie2 2War ni t er M as ng CurrentAlternator CurrentBatterie1Fil Voltag eAltern ato r Aquire S ig nal Diagnosis y1D i Bat t er i s agnos VoltageBatterie1Fil ePow e Com put r M ana nt gem e Aquire S ig nal CurrentBatterie2Fil Aquire S ig nal Com put ePow e r M ana gem e nt Bat t er y2D i a gnosi s VoltageBatterie2Fil Aquire S ig nal Diagnosis CurrentAlternatorFil Aquire S ig nal ePow e Com put r M ana gem e nt er nat A l t i a or D gnosi s VoltageAltern ator Fil Aquire S ig nal 10 5
Design Flow (2) • Generation of an ideal communication between the functional components – No delay or error handling considered. – Functional co-verification 11 Design Flow (3) • Creation of an architectural diagram in VCC RTOS PPC RTOS PPC RTOS PPC RTOS PPC RTOS PPC RTOS PPC RTOS PPC TTPController TTPController TTPController TTPController TTPController TTPController TTPController PPC_TTP Channel1 PPC_TTP Channel1 PPC_TTP Channel1 PPC_TTP Channel1 PPC_TTP Channel1 PPC_TTP Channel1 PPC_TTP Channel1 Channel2 Channel2 Channel2 Channel2 Channel2 Channel2 Channel2 TTP Channel 2 PPC_TTP Channel1 PPC_TTP Channel1 PPC_TTP Channel1 PPC_TTP Channel1 PPC_TTP Channel1 PPC_TTP Channel1 Channel2 Channel2 Channel2 Channel2 Channel2 Channel2 RTOS PPC RTOS PPC RTOS PPC RTOS PPC RTOS PPC RTOS PPC TTPController TTPController TTPController TTPController TTPController TTPController 12 6
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